10422189 (B.P.A.I. Oct. 28, 2009)

Ex Parte Musselman

Board of Patent Appeals and InterferencesOct 28, 2009

10422189 (B.P.A.I. Oct. 28, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte ROY GLENN MUSSELMAN ____________ Appeal 2008-005732 Application 10/422,189 Technology Center 2100 ____________ Decided: October 28, 2009 ____________ Before JOSEPH L. DIXON, LANCE LEONARD BARRY, and THU A. DANG, Administrative Patent Judges. BARRY, Administrative Patent Judge. DECISION ON APPEAL Appeal-2008-005732 Application 10/422,189 2 STATEMENT OF THE CASE The Patent Examiner rejected claims 1-10 and 13-16. The Appellant appeals therefrom under 35 U.S.C. Â§ 134(a). We have jurisdiction under 35 U.S.C. Â§ 6(b). INVENTION The invention at issue on appeal "us[es] clock bursting to minimize command latency in a logic simulation hardware emulator/simulation accelerator." (Spec. 1.) ILLUSTRATIVE CLAIM 14. A method for controlling the clock input to all latches within a design under test in a logic simulation hardware emulator, the hardware emulator comprising an emulation system coupled to a host workstation by a high-speed cable, the method comprising the steps of: encoding at the host workstation a predetermined number of clock cycles to run the emulation system; loading the encoded predetermined number of clock cycles into a plurality of signals within the high-speed cable; sending a trigger signal on the high-speed interface cable to capture the encoded predetermined number of clock cycles on the high-speed cable into a burst clock logic within the emulation system; decoding the encoded predetermined number of clock cycles within the burst clock logic; and enabling within the burst clock logic a clock enable signal for the predetermined number of clock cycles. Appeal-2008-005732 Application 10/422,189 3 PRIOR ART Ammann 4,975,869 Dec. 4, 1990 U.S. Patent application No. 10/422,189 (filed April 24, 2003), Specification, pp. 1-5, Appellant's Admitted Prior Art (AAPA). REJECTION Claims 1-10 and 13-16 stand rejected under 35 U.S.C. 103(a) as being unpatentable over AAPA and Ammann. ISSUE The Examiner admits that AAPA "does not teach . . . a burst clock logic; transmits the encoded predefined number of cycles to the burst clock logic . . . in combination with the control program that encodes the predefined number of cycles." (Ans. 4 (emphasis omitted.)) He finds, however, that Ammann's "logic to generate or to cycle signal 26A and other signals together with one or more counters mentioned are considered the burst-clock logic." (Id. 9.) The Appellant argues "that the passage cited by the Examiner discusses the bursting of data, not the bursting of a clock." (App. Br. 5.) Therefore, the issue before us is whether the Appellant has shown error in the Examiner's finding that AAPA and Ammann would have suggested bursting a clock in accordance with a number of encoded clock cycles. LAW "'A prima facie case of obviousness is established when the teachings from the prior art itself would appear to have suggested the claimed subject Appeal-2008-005732 Application 10/422,189 4 matter to a person of ordinary skill in the art.'" In re Bell, 991 F.2d 781, 783 (Fed. Cir. 1993) (quoting In re Rinehart, 531 F.2d 1048, 1051 (CCPA 1976)). FINDING OF FACT (FF) Ammann's "output signal from the flip-flop 24" (col. 5, l. 45) "starts a timer 26 which provides three sequential output signals 26A, 26B, and 26C, collectively referred to as event timing signals . . . ." (id. ll. 48-50). "The signal 26A, for example, decrements the byte count. The signal 26B strobes the memory 100 (FIG. 1) to read out the byte at the current address (not shown). The signal 26C increments the memory address[.]" (Id. ll. 51-54.) ANALYSIS Ammann discloses three event timing signals, 26A, 26B, and 26C. (FF.) None of the signals, however, controls the bursting of a clock. Instead, signal 26A decrements a byte count; signal 26B strobes a memory to read out the byte at the current address; and signal 26C increments the memory address. (FF.) Therefore, we agree with the Appellant "that the passage cited by the Examiner discusses the bursting of data, not the bursting of a clock." (App. Br. 5.) CONCLUSION Based on the aforementioned facts and analysis, we conclude that the Appellant has shown error in the Examiner's finding that AAPA and Ammann would have suggested bursting a clock in accordance with a number of encoded clock cycles. Appeal-2008-005732 Application 10/422,189 5 DECISION We reverse the rejection of claims 1-10 and 13-16. REVERSED llw IBM CORPORATION ROCHESTER IP LAW DEPT. 917 3605 HIGHWAY 52 NORTH ROCHESTER, MN 55901-7829