Ex Parte Murphy et al

Patent Trials and Appeals Board

Apr 30, 2019

13803015 - (D) (P.T.A.B. Apr. 30, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/803,015 03/14/2013
12675 7590 05/02/2019
Cesari & Reed, LLP - Seagate Technology LLC
1114 Lost Creek Boulevard
Suite 430
Austin, TX 78746
FIRST NAMED INVENTOR
Robert Dale Murphy
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1000-STLl 7420 4794
EXAMINER
GOLDSCHMIDT, CRAIG S
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
05/02/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
usptomail@cesari-reed.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ROBERT DALE MURPHY and
ROBERT WILLIAM DIXON 1
Appeal2018---007573
Application 13/803,015
Technology Center 2100
Before BRADLEY W. BAUMEISTER, SHARON PENICK, and
RUSSELL E. CASS, Administrative Patent Judges.
CASS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1, 2, 4--7, 10-12, 14--17, and 20, which constitute
all the claims pending in this application. Appeal Br. 2. 2 We have
jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part.
1 Appellants list Seagate Technology LLC as the real party in interest.
Appeal Brief filed February 7, 2018 ("Appeal Br.") 2.
2 Rather than repeat the Examiner's positions and Appellants' arguments in
their entirety, we refer to the above mentioned Appeal Brief, as well as the
following documents for their respective details: the Final Action mailed
June 7, 2017 ("Final Act."); the Examiner's Answer mailed May 18, 2018
("Ans."); and the Reply Brief filed July 18, 2018 ("Reply Br.").
Appeal2018---007573
Application 13/803,015
THE PRESENT INVENTION
The present invention is directed to an apparatus and method for
enabling a computer to enter and resume a hibernation state quickly.
Abstract. As Appellants' specification explains, computer systems may be
placed in a hibernation state in order to save power while preserving the
status of the operating system. Spec. ,r 11. When resuming from
hibernation, there may be a lapse between the time when the user request to
bring the computer out of hibernation and the time when the computer is
fully up and running. Id. Appellants' invention proposes to shorten this
time lapse by including hibernation controls on a data storage device used
with the computer that can independently determine the location of the
hibernation data at a first memory location without notification from a host.
Id. ,r 15. The hibernation controls may also assign the hibernation data to a
second memory location with a faster access time than the first memory
location. Id. ,r 17.
Claims 1, 2, and 10-12 are illustrative of the claims at issue:
1. An apparatus comprising:
a data storage device (DSD) including:
a circuit configured to:
determine a first memory location of
hibernation data at a first nonvolatile
memory in the DSD, without receiving an
indication of the first memory location from
a host, based on a hibernation partition of
the DSD; and
store the hibernation data to a second
memory location at a second nonvolatile
memory in the DSD.
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2. The apparatus of claim 1, further comprising an
interface configured to allow the DSD to be physically
removed from the host and to receive commands from
the host when the interface is coupled to the host.
10. The apparatus of claim 1, further comprising a
partition identification system including a partition table
that identifies a hibernation partition type associated with
the hibernation partition.
11. The apparatus of claim 10, further comprising the
circuit is configured to:
determine if the partition table has been altered;
and
when the partition table has been altered, repeat
determining a first memory location of hibernation
data without receiving an indication of the first
memory location from the host.
12. A method comprising:
scanning, via a data controller within a data
storage device (DSD) that is removable from a
host, a partition table within the DSD for an
indicator of a hibernation partition of a first
nonvolatile memory location in the DSD without
receiving an indication of the first memory
location from a host; and
storing data intended for the hibernation partition
of the first nonvolatile memory to a second
nonvolatile memory location of the DSD.
Appeal Br. 20-21 (Claims Appendix).
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Application 13/803,015
THE EXAMINER'S REJECTION
In the Final Office Action, the Examiner rejected claims 1, 2, 4--7, 10-
12, 14--17, and 20 as being unpatentable over Hanebutte (US 2008/0082743
Al; published April 3, 2008) in view of Puckette (US 6,385,721 Bl; issued
May 7, 2002).
ANALYSIS
Claims 1, 4-7, and 10
In rejecting claim 1, the Examiner relies primarily on Hanebutte,
which teaches a method for speeding up a computer's resumption from
hibernation by storing and retrieving hibernation data from a faster non-
volatile (NV) cache rather than a slower hard disk drive. Final Act. 2--4;
Hanebutte, Abstract. Hanebutte teaches that "caching and restoring the
memory content using the NV cache" can be performed "in an [ operating
system (OS)] transparent manner." Hanebutte ,r 28. This is carried out
using a "mapping table" that "correlate[ s] the cached data to the original
data which is expected to be written to the [hard] disk drive." Id. ,r 29.
When the system enters the hibernation state, instructions from the
operating system to save data on the hard disk drive "may be diverted to the
non-volatile cache by the storage driver" by using the correlations set forth
in the mapping table. Id. ,r,r 22, 29. Thus, "the mapping table helps to hide
the non-volatile cache from the OS." Id.
Hanebutte explains that the hibernation data also is written to the hard
disk drive at the address provided from the OS, which "does not represent a
performance penalty, [because] both devices may be served at the same time
and the writing of the data may be carried out in parallel." Id. ,r 32.
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Hanebutte further explains that when the system resumes from hibernation,
data may be read from the non-volatile cache back into the main memory
"without being known by the OS" using the mapping table. Id. ,r 29.
The mapping table of Hane butte is shown in Figure 5:
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-~---.L.~----......... --....---~----------~.-,...-----
1, 7,.·N.NDTE·.R.x':' tA,OOGO,}Rc~~~~:-l~CA-~ i NUi\t16ER o;:: ADO•~RAE'.}s:.·. SPEODN !-1\.t 1· ADDITIONAL
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Figure 5 shows the mapping table of Hane butte.
As shown in Figure 5 of Hane butte, the mapping table includes
multiple entries, each representing a block of data having its own index
number (0, 1, 2, etc.). Hanebutte ,r,r 30-31. Column 510 includes the
logical block address (LBA) of the block of data (also called a SCSI Request
Block (SRB)) on the hard disk drive, which is the location on the hard disk
where the operating system directs hibernation data to be saved, and
column 520 includes the size of the data block. Id. Column 530 includes
mapped addresses on the NV cache for the LB As shown in column 510. Id.
,r 31. By using this table, hibernation data may be written to addresses on
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the non-volatile cache ( column 530) without those addresses being known to
the operating system. Id. ,r 29.
The Examiner finds, inter alia, that Hanebutte discloses that
"hibernation data can be directed to the NVRAM cache" and "can still be
written through to the hard disk." Final Act. 3--4. In rejecting the claim, the
Examiner appears to be relying on the memory location of hibernation data
in the hard disk drive of Hane butte as the "first memory location" of claim 1
(although this is not entirely clear from the rejection) and the location of the
hibernation data in the NV cache of Hane butte as the "second memory
location" of claim 1. Final Act. 3--4. The Examiner further relies on
Hane butte's disclosure that storage in the NV cache can occur in an "OS
transparent" manner. Final Act. 3, 17-18.
Appellants argue that the portions of Hane butte cited by the Examiner
do not disclose writing data to the first memory location (the hard disk drive)
"without receiving an indication of the first memory location from a host,"
and that Hanebutte's disclosure that hibernation data can be written to
memory in an "OS transparent" mode does not teach this limitation. Appeal
Br. 6-10.
To the extent the Examiner relies on the hard disk drive of Hanebutte
as the "first memory location" of claim 1, we agree with Appellants that
Hanebutte does not teach writing data to that location "without receiving an
indication of' that memory location from a host, because the memory
location of data on the hard disk drive is provided by the operating system.
Hanebutte ,r,r 29, 32.
However, the error in the Examiner's determination does not end our
inquiry. Ifwe consider the NV cache of Hanebutte to be the "first memory
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location" of claim 1 instead of the "second memory location" ( as the
Examiner determined), Hanebutte still can be reasonably interpreted as
teaching this disputed limitation. As discussed above, Hanebutte teaches
that hibernation data is saved to a memory location in the NV cache (the first
memory location) without that address "being known by the OS."
Hane butte ,r 29. This is carried out by using the memory table of Figure 5 to
"hide the non-volatile cache from the OS" by including information that
maps locations on the hard disk (received from the OS) to locations on the
NV cache where data is to be stored. Id. Similarly, when the system
resumes, hibernation data may be read from the NV cache "without being
known by the OS." Id.
While the Examiner does not make this determination, we conclude
that if the "second memory location" of claim 1 is considered to be the hard
disk drive of Hane butte, Hane butte teaches "stor[ing] the hibernation data to
a second memory location at a second nonvolatile memory in the DSD," as
claim 1 requires. As discussed above, paragraph 32 of Hane butte teaches
that "data is written to the NV cache as well as the non-volatile storage
device," i.e., the hard disk drive. Hanebutte ,r 32.
Appellants make several additional unpersuasive arguments
distinguishing claim 1 from the prior art. More specifically, Appellants
argue that "Appellant[s'] claims and specification are directed to a system
where the data storage device itself is smart enough to locate where the host
has stored hibernation data, and copy or move it to another memory
location." Reply Br. 5---6 (emphasis in original). Claim 1, however, is
significantly broader than this description, and says nothing about having the
storage device copy or move the hibernation data to a second memory
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location. It only requires storing the hibernation data in a second memory
location at a nonvolatile memory in the DSD.
Appellants also argue that in Hane butte, "[ w ]hen writes of hibernate
data are to be performed to the NV cache, it is still based on receiving
[Small Computer System Interface Request Blocks (SRBs)] from the host."
Appeal Br. 7. The SRBs ( another name for the Logical Block Addresses
(LBAs)) received from the operating system, however, do not provide an
indication of the location at which the hibernation data is to be stored in the
NV cache (the claimed first memory location). They only provide an
indication of where the hibernation data is to be stored in the hard disk drive
( the claimed second memory location). Hane butte ,r,r 29, 31. The location
at which the hibernation data is to be stored in the NV cache comes from the
mapping table, which "hide[s] the non-volatile cache from the OS" and
determines the address on the NV cache in an "OS transparent manner."
Hane butte ,r,r 28-29. Thus, the hibernation data in Hanebutte is stored in a
"first memory location" (in the NV cache) without an indication of that
memory location from the host.
Finally, Appellants argue that Hanebutte does not teach determining
the first memory location "based on a hibernation partition of the DSD," as
set forth in claim 1. Appeal Brief 10. The Examiner, however, relies for
this limitation on Puckette, which teaches storing hibernation data in a
hibernation partition of a memory. Final Act. 4--5; Ans. 6-7, 21; Puckette
4:42--46, 6: 16-7:8. The Examiner finds that Puckette's storing and
accessing of hibernation data in a hibernation partition meets the claim
element of determining a first memory location "based on a hibernation
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partition" because "accessing the hibernation data in the hibernation
partition would be 'based on a hibernation partition.'" Ans. 21.
Appellants acknowledge that Puckette discloses a hibernation
partition, but argue that "the combined teachings of the references still rely
on host indications to locate the hibernate data, rather than doing so based on
a hibernation partition without host indications." Appeal Br. 10. See Reply
Br. 13-14.
We agree with the Examiner that the limitation of "determining a first
memory location 'based on a hibernation partition"' would have been
obvious over the cited prior art. In this connection, we note that neither the
claims nor the Specification defines precisely what it means to determine a
first memory location of hibernation data "based on" a hibernation partition.
Under the broadest reasonable interpretation of the claim language, we
interpret this phrase broadly to cover a situation where a hibernation
partition is used in any manner in determining the first memory location.
Puckette teaches storing hibernation data in a hibernation partition so
that this data can be "hidden from the operating system so that it [cannot] be
accessed or corrupted." Puckette 4:43-46. It would have been obvious to
use a hibernation partition to store hibernation data, as taught by Puckette, in
the system of Hanebutte in order to prevent the hibernation data from being
accessed or corrupted by the operating system, as Puckette teaches.
In such a combination, the mapping table in Hanebutte would
determine the first memory location ( column 530 of the mapping table of
Figure 5) based on the address of hibernation data in the hibernation
partition ( column 510 of the mapping table of Figure 5). In this
combination, because the address of hibernation data in column 510 would
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be in a hibernation partition, memory location 530 would be determined
"based on" a location in a hibernation partition.
Having considered the Examiner's rejection of claim 1 in light of the
Appellants' arguments and the evidence of record, we conclude that claim 1
is unpatentable over Hane butte and Puckette. We, therefore, sustain the
obviousness rejection of that claim. Because our reasoning differs from that
of the Examiner, we designate the rejection of claim 1 as constituting a new
ground pursuant to our discretionary authority under 37 C.F.R. § 4I.50(b).
For the reasons set forth by the Examiner, as modified by our above-
noted alternative reasoning, we likewise sustain the Examiner's rejection of
claims 4 and 10, which Appellants do not argue separately. See Appeal Br.
12-15.
We choose not to exercise our discretionary authority to issue a new
ground of rejection with respect to dependent claims 5-7. As such, and
because we would reverse the obviousness rejection of claim 1 under the
Examiner's rationale, we reverse the rejection of claims 5-7.
Claim 2
In rejecting claim 2, the Examiner determines that it would have been
obvious to make the data storage device separable from the host. Ans. 7-8,
22 ( citing MPEP 2144. 04(V)( C) to illustrate that making components
separable is an example of "common practices [that] the court ha[ ve] held
normally require only ordinary skill in the art and hence are considered
routine expedients"). The Examiner reasons that the "[hard disk drive
(HDD)] and NV Cache (DSD) are off-the-shelf computer products, and the
ability to detach a hard disk and a flash drive from a computer [was]
notoriously well known in the art, as they [were] often designed to be
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removable, and [were] interfaced through common connectors such as AT A,
SATA, SCSI, USB, etc." Ans. 7 (emphasis omitted). In the Examiner's
Answer, the Examiner further relies on Bondurant (2009/0013129 Al;
published January 8, 2009), which discloses "a removable storage array
(DSD) that can be separated from a host." Ans. 22 ( citing Bondurant ,r 51 ).
Appellants argue that Hanebutte "does not depict the disk controller,
HDD, and NV cache as part of a distinct data storage device that is
removable from a host," and that "it [was] much more common for a hard
disk drive and a nonvolatile cache to be separate components." Appeal
Br. 13-14. Appellants further argue that the addition of Bondurant qualifies
as a new ground of rejection, and that Bondurant does not show a distinct
removable storage device with different types of memories. Reply Br. 2, 16.
We agree with the Examiner's obviousness rejection of claim 2. We
find that it was well-known to make a data storage device removable in
order to, for example, allow the storage device to be serviced or replaced, or
to allow memory to be added, as in Bondurant. Appellants do not dispute
this. See, e.g., App. Br. 5---6.
We also find that it would have been obvious to include both a hard
disk drive and an NV cache as part of the "data storage device" of the claim.
Appellants' Specification explains that the term "data storage device" should
be understood broadly. See Spec. ,r 13 (explaining that the data storage
device "may be a hybrid device, a solid state device, an optical device, a
magnetic device, any other type of data storage device, or any combination
thereof'). Combining two well-known memory devices into a single data
storage device is simply a "combination of familiar elements according to
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known methods" that "does no more than yield predictable results." KSR
Int'! Co. v. Teleflex, Inc., 550 U.S. 398,416 (2007).
Thus, we conclude that claim 2 is unpatentable over Hanebutte,
Puckette, and Bondurant. Since we have designated the rejection of claim 1
as a new ground of rejection, and claim 2 depends from claim 1, this too
constitutes a new ground of rejection.
Claim 11
In rejecting claim 10 (upon which claim 11 depends), the Examiner
finds that Puckette discloses "a partition identification system including a
partition table that identifies a hibernation partition type associated with the
hibernation partition." Final Act. 7. In rejecting claim 11, the Examiner
states, as follows:
Hane butte and Puckette disclose the apparatus of claim 10, and
Hane butte further discloses determining if the partition table
has been altered; and when the partition table has been altered,
repeat determining a first memory location of hibernation data
without receiving an indication of the first memory location
from the host (Figure 6). The system creates a mapping table
(partition table) to associate hibernation file locations in the NV
cache with those in the HDD. After each new entry has been
added (partition table has been altered), the process repeats for
as long as there are more entries to be added; each time the new
entry is added, the storage driver determines the location of a
hibernation file in the HDD (first memory location) in an OS
transparent manner (without receiving an indication from the
host).
Final Act. 7-8 ( emphasis omitted).
In response, Appellants argue that the mapping table of Hane butte is
not a partition table. According to Appellants:
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A partition table broadly identifies areas of memory that have
been categorized for different uses, and does not individually
identify files or file chunks. Conversely, the mapping table of
Hane butte is a direct mapping of files from the LB As on the
hard disk where the host stored them for hibernation, to the
memory addresses in the NV cache where they were also
stored. These are completely different tables that serve
completely different functions, and they are not
interchangeable.
Appeal Br. 15 ( emphasis omitted). Appellants further argue that while
"Puckette does describe a partition table," it does not teach or suggest
"determin[ing] if the partition table has been altered; and when the partition
table has been altered, repeat determining a first memory location of
hibernation data without receiving an indication of the first memory location
from the host," as set forth in claim 11. Id. at 16.
We agree with Appellants that the Examiner has not set forth a
sufficient basis to conclude that a person of ordinary skill would have
combined Hanebutte and Puckette to achieve the invention of claim 11. We
agree that a person of ordinary skill would understand a "partition table" to
be distinct from Hane butte's mapping table in Figure 5 because a partition
table identifies broad areas of memory categorized for different uses, and not
simply individual data addresses. This understanding of a partition table is
supported by Puckette, which describes a "partition table" as a table "that
contains information pertaining to the size, type and location of disk
partitions," and "partitions" as divisions of a hard disk, each "having an
amount of storage selectable at the time of creation of the partition."
Puckette Col. 4: 17-24; 50-52.
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Thus, the "partition table" of Puckette is not substitutable for the
"mapping table" of Hane butte. Additionally, the Examiner has failed to
explain how a person of ordinary skill would have modified Hanebutte to
use Puckette's table in place of the mapping table. Nor has the Examiner
provided a reason or motivation for a person of ordinary skill to do so.
Consequently, we reverse the Examiner's rejection of claim 11.
Claim 12
Claim 12 includes many limitations that are substantially similar to
those in claims 1 and 2, but differs from those claims in that it includes the
limitation of "scanning, via a data controller within a data storage device
(DSD) ... a partition table within the DSD for an indicator of a hibernation
partition of a first nonvolatile memory location in the DSD without receiving
an indication of the first memory location from a host." Appeal Br. 21
( Claims Appendix).
The Examiner finds that Puckette teaches scanning a partition table of
a DSD for an indicator of a hibernation partition of a first nonvolatile
memory. Final Act. 10, 14--15. The Examiner states that it would have been
obvious "to modify the hibernation system of Ha[n]ebutte such that the
hibernation data was stored in a dedicated partition, as in Puckette, because
Puckette suggests that this would [have allowed] a machine to be booted
from the hibernation file using a secure hibernation boot utility." Final
Act. 10-11, 15; Ans. 12, 16-17. Appellants respond that "the combined
references do not teach or suggest the DSD controller scanning a partition
table for a hibernation partition to locate the hibernation data, all without an
indication of the location from the host." Appeal Br. 16.
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We agree with Appellants that the cited portions of Hanebutte and
Puckette do not teach "scanning, via a data controller within a data storage
device (DSD) ... a partition table within the DSD for an indicator of a
hibernation partition of a first nonvolatile memory location in the DSD
without receiving an indication of the first memory location from a host."
As discussed above in connection with claim 11, Hanebutte discloses
scanning a mapping table, but the mapping table of Hane butte is different
from a "partition table," as recited in the claims. Puckette teaches a partition
table, but the portions cited by the Examiner do not teach scanning the
partition table for an indicator of a hibernation partition "without receiving
an indication of the first memory location from a host," as claim 12 requires.
See Puckette Col. 4: 17-24; 50-52.
As discussed above in connection with claim 11, the Examiner fails to
explain how a person of ordinary skill would have modified Hanebutte to
use Puckette' s table in place of the mapping table in Figure 5 of Hane butte,
or provide a sufficient reason or motivation for a person of ordinary skill to
do so. Consequently, we reverse the Examiner's rejection of claim 12. We
also reverse the Examiner's rejections of claims 14--17 and 20, which are
dependent on claim 12 or recite similar limitations.
DECISION
We affirm the Examiner's rejection of claims 1, 2, 4, and 10.
We reverse the Examiner's rejection of claims 5-7, 11, 12, 14--17,
and 20.
Because reasoning relied on by the Board to sustain the rejection of
claims 1, 2, 4, and 10 differs from the reasoning relied on by the Examiner,
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we designate our affirmance of the modified rejections as constituting a new
ground of rejection pursuant to 37 C.F.R. § 4I.50(b).
Rule 37 C.F.R. § 4I.50(b) provides "[a] new ground of rejection
pursuant to this paragraph shall not be considered final for judicial review."
Rule 37 C.F.R. § 41.50(b) also provides that Appellants, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
( 1) Reopen prosecution. Submit an appropriate amendment of
the claims so rejected or new Evidence relating to the claims so
rejected, or both, and have the matter reconsidered by the
Examiner, in which event the proceeding will be remanded to
the examiner. The new ground of rejection is binding upon the
examiner unless an amendment or new Evidence not previously
of Record is made which, in the opinion of the examiner,
overcomes the new ground of rejection designated in the
decision. Should the examiner reject the claims, appellant may
again appeal to the Board pursuant to this subpart.
(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same Record. The request
for rehearing must address any new ground of rejection and
state with particularity the points believed to have been
misapprehended or overlooked in entering the new ground of
rejection and also state all other grounds upon which rehearing
is sought.
Pursuant to 3 7 C.F .R. § 1.13 6( a )(1 )(iv), no time period for taking any
subsequent action in connection with this appeal may be extended. See
37 C.F.R. § 4I.50(f).
AFFIRMED-IN-PART
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37 C.F.R. § 4I.50(b)
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