Ex Parte Muraki

Patent Trial and Appeal Board

Jun 27, 2014

12028965 (P.T.A.B. Jun. 27, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD

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Ex parte YOSUKE MURAKI
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Appeal 2012-002413
Application 12/028,965
Technology Center 2100
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Before ROBERT E. NAPPI, JOHN A. EVANS, and
CHARLES J. BOUDREAU, Administrative Patent Judges.

BOUDREAU, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The real parties-in-interest are identified as Sony Corporation and Sony
Electronics Inc. (App. Br. 3.)
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STATEMENT OF THE CASE
Appellant’s claimed invention relates to a memory system, and more
particularly, to a removable, nonvolatile memory system. (See Spec. ¶ 1.)
Claims 1 and 11, reproduced below, are representative of the subject
matter on appeal:
1. A removable nonvolatile memory system comprising:
storing read data onto a memory portion of a memory
device; and
accessing the memory portion including:
reading the read data from the memory portion, and
writing predetermined data onto the memory portion after
reading the memory portion.

11. A removable nonvolatile memory system
comprising:
a memory portion of a memory device for storing read
data; and
a controller device coupled to the memory device for
accessing the memory portion including:
reading the read data from the memory portion, and
writing predetermined data onto the memory portion after
reading the memory portion.

Claims 1-3, 5-7, 9, 11-13, 15-17, and 19 stand rejected under
35 U.S.C. § 102(e) as being anticipated by Tremaine (US 2007/0288707 A1,
published Dec. 13. 2007). (See Ans. 5-9.)
Claims 4 and 14 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tremaine and Conley (US 2006/0136656 A1; published
June 22, 2006). (See Ans. 9-10.)
Claims 8, 10, 18, and 20 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Tremaine, Arimilli (US 6,675,270 B2; issued Jan. 6,
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2004), and Roohparvar (US 6,691,204 B1; issued Feb. 10, 2004). (See Ans.
10-12.)

ANALYSIS
Claims 1 and 11
The Examiner finds Tremaine teaches a removable, nonvolatile
memory system that includes storing read data onto a memory portion of a
memory device. (Ans. 5 (citing Tremaine ¶¶ 15, 68, 70, 71).) The
Examiner further finds Tremaine discloses accessing the memory portion,
including reading the read data from the memory portion (Ans. 5 (citing
Tremaine Fig. 9, block 904; and ¶ 58, ll. 1-8)) and writing predetermined
data onto the memory portion after reading the memory portion (Ans. 6
(citing Tremaine Fig. 9, blocks 910, 912, 914; and ¶ 59, ll. 1-14)).
Appellant argues Tremaine does not disclose “accessing the memory
portion including writing predetermined data onto the memory portion after
reading the memory portion,” as recited in claims 1 and 11, but instead “only
discloses correcting invalid data, modifying data, and adding error correction
bits after reading data.” (App. Br. 11.) According to Appellant:
The Tremaine block 908 for correcting invalid data
cannot be writing predetermined data because the data to be
written, if any, is conditionally altered by correction during the
Tremaine RMW [read-modify-write] memory access . . . .
The Tremaine modify pipeline 721 does not write
predetermined data because the modification to be written is
determined during the Tremaine RMW memory accessing
while operating on the Tremaine memory read data . . . .
The Tremaine block 912 for adding error correction bits
does not write predetermined data because the data to be written
is altered by addition of the Tremaine error correction bits
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developed by the Tremaine EDC code generation block 719
during the Tremaine RMW memory accessing . . . .
(App. Br. 11-12.)
We do not find Appellant’s argument persuasive.
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification. See In re Zletz, 893 F.2d
319, 321 (Fed. Cir. 1989) (during patent examination the pending claims
must be interpreted as broadly as their terms reasonably allow). The claims
on appeal do not include any limitation as to how far in advance the data
must be determined before writing. In the absence of such a limitation, we
find that any data that are determined before being written can reasonably be
considered “predetermined.”
Figure 9 of Tremaine, cited by the Examiner, clearly illustrates
writing (block 914) occurring after the data-correction, modification, and
addition-of-error-correction-bits steps have determined the data to be
written. (See also Tremaine ¶ 59 (“As described previously, the data being
written is either the data modified by the ALU 717 with error correction bits
added, or data from the write data queue 711 with error correction bits
added.”).) So although Appellant may be correct that the three specific
Tremaine blocks 908, 721, and 912 do not write predetermined data (see
App. Br. 11-12), Tremaine block 914 for writing to memory devices occurs
after those other blocks and involves writing of the data determined in those
blocks—i.e., writing of predetermined data.
Thus, contrary to Appellant’s argument, we find that Tremaine
teaches writing “predetermined data” onto a memory portion after reading
the memory portion. The fact that data may be altered, or determined,
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“during the Tremaine RMW memory accessing” does not lead us to any
different result.
Appellant also argues “Tremaine does not address the purpose for the
claimed invention as explained on Specification paragraph [0034].” (App.
Br. 11.)
The Examiner responds that “the purpose described in [0034] of the
current invention is not cited in the claims.” (Ans. 14.) We agree.
Appellant’s claims in this appeal are not limited to data protection, let alone
“robust and reliable data protection” or a “low cost, low power and high
performance data protection system.” “Eliminating . . . data” is likewise not
an element of any of the claims on appeal. Accordingly, we are also not
persuaded by Appellant’s argument concerning the “purpose” of the
invention.
Appellant further argues that the Examiner “has used an unreasonably
broad interpretation of the claim term ‘predetermined data’” (App. Br. 12),
pointing to paragraph 31 of the specification. The cited paragraph, which
relates to an embodiment shown in Figure 5 of Appellant’s application,
states that “[t]he predetermined data pattern is defined as all ones pattern, an
alternating zero and one pattern, or a random zeros or ones pattern.” (Spec.
¶ 31.)
Again, we do not find Appellant’s argument persuasive. The claims
on appeal do not recite writing a predetermined data “pattern,” and there is
no indication in Appellant’s specification that the statement in paragraph 31
is intended to limit the claim term “predetermined data” generally to
particular patterns of predetermined data.
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Accordingly, in view of the cited teachings of Tremaine, we are not
persuaded of error in the Examiner’s finding that claims 1 and 11 are
anticipated by Tremaine.2
Claim 6
Claim 6 recites, in part, “writing predetermined data different from the
read data onto the memory portion immediately after reading the memory
portion.” Referring again to Figure 9 and paragraph 59 of Tremaine, the
Examiner finds that Tremaine also anticipates claim 6. (Ans. 7.)
Appellant argues that “writing predetermined data different from the
read data onto the memory portion immediately after reading the memory
portion is not disclosed in Tremaine. Tremaine, instead, only discloses
correcting invalid data immediately after reading data as shown in Tremaine
FIG. 9.” (App. Br. 13.) Appellant further argues that “[t]he Tremaine
blocks 906 and 908 are the only blocks immediately following the Tremaine
block 904 to read data.” (Id.)
In response, the Examiner explains as follows:
Tremaine Fig. 9, block 914 depicts writing the data to memory
devices. The writing occurs at the end of the read-modify-
command, which is an atomic command and therefore any
intermediate processes are a part of the command and not
separate. Therefore the write to memory devices does occur
immediately after the read, as within the scope of the claim.
(Ans. 14-15.)

2 In the event of further prosecution, claims 1-10 should be examined for
indefiniteness under 35 U.S.C. § 112; although those claims are each
directed to a “removable nonvolatile memory system,” each of the elements
of those claims is a method step. See IPXL Holdings v. Amazon.com, 430
F.3d 1377, 1384 (Fed. Cir. 2005) (holding invalid for indefiniteness a claim
directed to both a system and a method).
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We are not persuaded of any error in the Examiner’s finding. Figure 9
of Tremaine depicts a process flow that includes both a read operation
(block 904) and a write operation (block 914) that writes “either the data
modified by the ALU 717 with error correction bits added, or data from the
write data queue 711 with error correction bits added.” (Tremaine ¶¶ 58,
59.) There is no suggestion that the process flow is discontinuous or that
there is any pause that would cause the writing step to take place other than
“immediately,” as required by claim 6. Moreover, regardless of whether it is
the “data modified by the ALU 717 with error correction bits added” or the
“data from the write data queue 711 with error correction bits added” that
are written, the addition of the error correction bits renders the data being
written “different from the read data,” as required by claim 6.
Appellant also again raises the argument that the claimed
predetermined data is distinguishable over the Tremaine written data based
on the definition of “predetermined data pattern” in paragraph 31 of the
specification. For the reasons stated in the discussion of that argument in
connection with claim 1 above, we are not persuaded by that argument.
Accordingly, we are not persuaded of error in the Examiner’s finding
that claim 6 is anticipated by Tremaine.
Claims 2, 3, 5, 7, 9, 12, 13, 15-17, and 19
Appellant does not provide additional substantive arguments
regarding the patentability of dependent claims 2, 3, 5, 7, 9, 12, 13, 15-17,
and 19, but cites to In re American Academy of Science Tech Center, 367
F.3d 1359 (Fed. Cir. 2004) and Therasense, Inc. v. Becton, Dickinson & Co.,
593 F.3d 1325 (Fed. Cir. 2010) and indicates that the respective dependent
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claims stand or fall with the independent claims from which they depend.
(App. Br. 13.)
For the reasons stated above in connection with independent claims 1,
6, and 11, we are also not persuaded of error in the Examiner’s finding that
dependent claims 2, 3, 5, 7, 9, 12, 13, 15-17, and 19 are also anticipated by
Tremaine.
Claims 4, 8, 14, and 18
Appellant does not provide additional substantive arguments
regarding the patentability of dependent claims 4, 8, 14, and 18, but cites to
In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992) and indicates that those
claims stand or fall with the independent claims from which they
respectively depend. (App. Br. 14-16.)
For the reasons stated above in connection with independent claims 1,
6, and 11, along with the teachings of the cited references as found by the
Examiner, we are not persuaded of error in the Examiner’s findings that
dependent claims 4 and 14 are obvious over the combination of Tremaine
and Conley and that dependent claims 8 and 18 are obvious over the
combination of Tremaine, Arimilli, and Roohparvar.
Claims 10 and 20
Appellant indicates that claims 10 and 20 also stand or fall with the
independent claims from which they depend and cites again to In re Fritch
(App. Br. 16). Appellant additionally argues that the cited references do not
teach or suggest the claim limitation of “selectively not writing the
predetermined data onto a further memory portion of the memory device”
recited in claims 10 and 20. (App. Br. 16.) According to Appellant, Arimilli
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instead “teaches writing only the modified beats of data, which is not
selectively writing the claimed predetermined data onto the claimed further
memory portion of the memory device” (id.), and Roohparvar instead “only
teaches selectively terminating bursts during read accesses to the
Roohparvar synchronous flash memory, but not selectively writing the
claimed predetermined data” (id. at 17).
The Examiner responds as follows: “In Arimilli col. 5 lines 12-8,
only modified beats of the data are sent to the memory controller. Therefore
Arimilli selects not to write certain repetitious data and chooses to send
others, reducing latency time. Therefore Arimilli discloses the subject
matter of the limitation.” (Ans. 16-17.)
Appellant does not point to any support in the specification
corresponding to claims 10 and 20, and it is unclear what exactly is intended
by the limitation “writing the predetermined data . . . includes selectively not
writing the predetermined data” recited in those claims. Nonetheless, the
broadest reasonable interpretation of that claim limitation would at minimum
encompass writing certain data and not writing other data. Accordingly, we
see no error in the Examiner’s finding that the claim language would read
upon Arimilli’s writing of only modified beats of data—which, by virtue of
being “modified,” would appear to be “different from the read data,” as
recited in claims 10 and 20.
Therefore, and in view of the reasons stated above in connection with
independent claims 6 and 11, we are not persuaded of error in the
Examiner’s finding that dependent claims 10 and 20 are obvious over the
combination of Tremaine, Arimilli, and Roohparvar.

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DECISION
The rejection of claims 1-3, 5-7, 9, 11-13, 15-17, and 19 under
35 U.S.C. § 102(e) is affirmed.
The rejections of claims 4, 8, 10, 14, 18, and 20 under 35 U.S.C.
§ 103(a) are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED

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