Ex Parte Munjuluri et al

Patent Trial and Appeal Board

Mar 26, 2018

14137378 (P.T.A.B. Mar. 26, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/137,378 12/20/2013 Bala Nagendra Raja Munjuluri
57579 7590 03/28/2018
MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES
1255 Crescent Green
Suite 200
CARY, NC 27518
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1012-0796 I 2013P50831
us
7030
EXAMINER
ROCHE, JOHN B
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
03/28/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
official@mbhiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BALA NAGENDRA RAJA MUNJULURI and
PRAKASH NAY AK
Appeal2017-008216
Application 14/13 7 ,3 7 81
Technology Center 2100
Before THU A. DANG, DENISE M. POTHIER, and
JAMES W. DEJMEK, Administrative Patent Judges.
DEJMEK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1-20. We have jurisdiction over the pending claims under 35
U.S.C. § 6(b).
We affirm-in-part.
1 Appellants identify INFINEON TECHNOLOGIES AG as the real party in
interest. Br. 2.
Appeal2017-008216
Application 14/137,378
STATEMENT OF THE CASE
Introduction
Appellants' disclosed and claimed invention is directed to "techniques
for verification of instructions executing a task on a processor." Spec. i-f 4.
In the Specification, Appellants describe code flow control methods wherein
a signature value may be passed from one routine to another and the routine
receiving the signature may perform a check to ensure the routine was
invoke correctly. Spec. i-f 25. According to the Specification, the disclosed
approach may be used for secure processing. Spec. i-fi-1 11, 57.
Claim 1 is exemplary of the subject matter on appeal and is
reproduced below with the disputed limitations emphasized in italics:
1. A device, comprising:
a processor; and
a hardware component, wherein the processor is
configured to verify execution of at least one task expressed by
high-level instructions, and wherein a single high-level
instruction, when executed, is configured to cause the processor
to:
directly access the hardware component to store an
address where a signature value is stored;
directly access the hardware component to modifY
the stored signature value to generate a verification value;
and
store the generated verification value at the address
as an updated signature value.
The Examiner's Rejections
1. Claims 1-12 and 14--20 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Devins et al. (US 6,427,224 Bl; July 30, 2002)
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Application 14/137,378
("Devins") and Gammel et al. (US 2012/0246452 Al; Sept. 27, 2012)
("Gammel"). Final Act. 2-9.
2. Claim 13 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Devins, Gammel, and Hotaka (US 2002/0001233 Al;
Jan. 3, 2002). Final Act. 9-10.
ANALYSIS 2
Claims 1-10, 12, and 13
Appellants assert Devins is not analogous art to the claimed invention
and, therefore, is not properly relied on by the Examiner in rejecting the
pending claims. Br. 4--9. In particular, Appellants argue Devins describes
using verification software for testing system-on-chip (SOC) circuit level
designs. Br. 5. Appellants contend Devin's field of endeavor---circuit
design verification-is different from the verification of instructions
executing a task, which Appellants assert is the subject of the claimed
invention. Br. 5; see also Spec. i-f 4 ("[t]his disclosure is directed to
techniques for verification of instructions executing a task on a processor").
Additionally, Appellants assert Devins is not reasonably pertinent to the
particular problems facing the inventors of the claimed invention. Br. 6-7.
Specifically, Appellants assert the inventors of the claimed invention "were
concerned with detecting undesired instructions or altered sequences of
process code execution" whereas Devins "is concerned with
2 Throughout this Decision, we have considered the Appeal Brief, filed
October 24, 2016 ("Br.") the Examiner's Answer, mailed November 30,
2016 ("Ans."); and the Final Office Action, mailed May 19, 2016 ("Final
Act."), from which this Appeal is taken. Appellants did not file a Reply
Brief.
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testing/verifying complex chip circuit designs." Br. 6-7 (emphasis omitted).
Appellants argue that one addressing the detection of undesired instructions
or altered sequences of process code would not have been drawn to Devins' s
approach to improving the efficiency of chip design verification. Br. 7.
A reference is analogous art to the claimed invention if: (1) the
reference is from the same field of endeavor as the claimed invention (even
if it addresses a different problem); or (2) the reference is reasonably
pertinent to the problem faced by the inventor (even if it is not in the same
field of endeavor as the claimed invention). In re Bigio, 381F.3d1320,
1325 (Fed. Cir. 2004). In order for a reference to be "reasonably pertinent"
to the problem, it "logically would have commended itself to an inventor's
attention in considering his problem." In re Icon Health and Fitness, Inc.,
496 F.3d 1374, 1379-80 (Fed. Cir. 2007) (quoting In re Clay, 966 F.2d 656,
658 (Fed. Cir. 1992).
Devins "relates to the testing of computer system designs by software
simulation, and more particularly to a verification methodology which
increases the efficiency of verification of system-on-chip (SOC designs
which include an embedded processor." Devins, col. 1, 11. 25-29. Devins
describes that in order to avoid costs associated with "first implementing
designs in hardware to verify them," verification has moved increasingly
towards a software simulation approach. Devins, col. 1, 11. 41--44. Devins
discloses that verification software must be developed to cover a sufficient
number of test cases to fully exercise the design in order to achieve
"acceptably bug-free designs." Devins, col. 1, 11. 62-64.
Thus, each test case in Devins may represent the execution of a task or
function of the target design. Additionally, an ordinarily skilled artisan
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would understand that the simulation software must execute properly in
order to produce reliable simulation results. Accordingly, we agree with the
Examiner that Devins is reasonably pertinent to the problem faced by
Appellants-i.e., verifying the execution of a task. See Spec. i-f 4.
Appellants also assert a "skilled person looking to improve the Devins
invention would not tum to Gammel due to their unrelated fields of
application." Br. 11. Specifically, Appellants contend Gammel is not
concerned with SOC chip design verification, but rather with unexpected
execution of a given design. Br. 7.
We do not find Appellants' arguments persuasive of error. As
discussed, an ordinarily skilled artisan simulating the chip design of Devin
using verification software would want to ensure that the software is
executing properly such that simulation results are reliable. We agree with
the Examiner that one of ordinary skill in the art would modify the
verification software of Devins with the signature update functionality of
Gammel to ensure the proper operation of verification software. See Final
Act. 4.
Appellants also argue that Gammel, as relied on by the Examiner,
fails to teach a single high-level instruction configured to cause a processor
to (i) access a hardware component to store an address where a signature
value is stored; (ii) access the hardware component to modify the stored
signature value to generate a verification value; and (iii) store the generated
verification value at the address as an updated signature value. Br. 9--11. In
particular, Appellants assert that rather than teaching a single instruction,
Gammel discloses a combination of instructions and splitting instructions
into multiple steps. Br. 10 (citing Gammel i-fi-1 7, 61---62, Fig. 3).
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Gammel describes the premise of instruction signatures is that while a
program is running, executed instructions are summed in a checksum (i.e.,
signature) and the signature is checked against reference values at prescribed
positions in the program's execution. Gammel i-f 2. Gammel describes an
approach wherein the operation codes (opcodes) of the instructions can be
added to form a checksum (signature). Gammel i-f 4. Thus, with the
execution of each instruction, the opcode value of the instruction may be
added (or Exclusive-ORed) to the contents of a register to create an updated
checksum (signature). Gammel i-f 4. Gammel describes that for programs
having branches in the program flow (i.e., conditional jumps), the signature
value may dependent upon which path was taken. Gammel i-f 5.
Gammel discloses it is known that superfluous instructions may be
added by the compiler to certain branches such that the signatures within the
different branches, which can be taken by a program, may be oriented to
each other. Gammel i-f 5. Rather than adding superfluous instructions,
Gammel discloses using code transformations as part of the instruction
signature method. Gammel i-f 7. Gammel states "[ t ]he effect achieved by
the determination of the modified instruction sequence is that the execution
of the modified instruction sequence results in the calculation of the target
signature value." Gammel i-f 8. In other words, superfluous (explicit)
instructions are not needed to achieve the orientation of the signature value
across various branches of program execution. The signature update is
performed for each instruction of the modified instruction sequence (i.e., the
transformed code). Gammel i-f 9. Gammel expressly discloses "all
instructions are used in the signature calculation using the same method or
the same calculation specification." Gammel i-f 9.
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Figure 3 of Gammel is illustrative and is reproduced below:
FIG 3
Figure 3 of Gammel provides an example of a code transformation using
replacement. Gammel i-f 33. As shown in Figure 3, a code instruction (ADD
R3, 2468) is replaced with two instructions (ADD R3, 1330 and ADD R3,
1138). Gammel describes the argument is broken down "so that the result
remains the same [(i.e., a constant value of 2468 is added to register R3)] but
the signature retains the desired target value." Gammel i-f 61. By splitting
the instruction on the left side of Figure 3 into two instructions "allows the
instruction signature to be altered (updated) such that precisely the
functionality of an explicit signature update instruction is implemented."
Gammel i-f 62.
Appellants' arguments mischaracterize the teachings of Gammel. As
discussed above, with reference to Figure 3 of Gammel, each of the
instructions on the right hand side of Figure 3 is a single high-level
instruction that causes the signature value to be updated in the disclosed
manner (e.g., adding the associated opcode for the ADD instruction) to a
signature register. See Gammel i-f 4. Thus, contrary to Appellants'
assertions, we find Gammel teaches a single high-level instruction that,
when executed, causes the processor to (i) access a hardware component to
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store an address where a signature value is stored; (ii) access the hardware
component to modify the stored signature value to generate a verification
value; and (iii) stored the generated verification value at the address as an
updated signature value., as recited in claim 1.
Additionally, Appellants argue Gammel fails to teach "a control
register configured to hold control data unrelated to processing the task," as
recited in independent claim 5. Br. 11-12. Appellants contend Gammel's
disclosure that it is possible to dispense with explicit write access operations
to the signature register teaches "eliminating the need for write access to the
alleged control register, i.e., the signature register." Br. 11-12 (citing
Gammel i-f 9, emphasis omitted).
Contrary to Appellants' assertions, Gammel does not teach
eliminating the control register (i.e., the signature register). Rather, Gammel
teaches by using the disclosed code transformation, the need for superfluous
instructions to update the signature value may be eliminated, but that the
signature value is still being calculated and updated and stored in the
signature register. Gammel i-fi-14, 7, 9; see also Gammel i-fi-147-57, 61---65.
Thus, Gammel teaches a control register (i.e., a signature register)
configured to hold control data unrelated to processing the task (i.e., the
signature value).
For the reasons discussed supra, we are unpersuaded of Examiner
error. Accordingly, we sustain the Examiner's rejection of independent
claims 1 and 5. Additionally, we sustain the Examiner's rejections of claims
2--4, 6-10, 12, and 13, which depend directly or indirectly therefrom and
were not argued separately. See 37 C.F.R. § 41.37(c)(l)(iv)(2016).
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Claims 11 and 14-20
Claim 11 depends from claim 5 and recites "a process register
configured to receive process data, the process data being generated or used
when performing the associated operations to process the task." The
Examiner finds Gammel teaches the claimed process register. Final Act. 8
(citing Gammel i-f 15).
Appellants assert the Examiner's rejection of claim 11 is inconsistent
with the rejection of claim 5, for which the Examiner finds Devins teaches
instruction code to process the claimed task. Br. 12-13 (citing Final Act. 5).
Appellants argue the Examiner has not explained how a process register, as
identified by the Examiner, is configured and used to process the task
disclosed by Devins. Br. 13. Further, Appellants argue Gammel, as relied
upon by the Examiner, fails to teach a process register configured for use in
performing the operations associated with processing the task. Br. 13 (citing
Gammel i-f 15). Specifically, Appellants contend Gammel describes
assigning a constant value to a register without the constant value being used
for processing useful data. Br. 13 (quoting Gammel i-f 15).
The Examiner merely responds that "the value assigned to the register
is used to determine whether modification took place." Ans. 16.
On this record, we agree with Appellants that the Examiner has not
shown by a preponderance of evidence that Gammel, alone or in
combination with Devins, teaches or suggests the limitation of claim 11. In
particular, by indicating the value stored in the register is not used for
processing the useful data (i.e., data used in the execution of the task),
Gammel suggests the register is a control register, rather than a process
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register. Accordingly, we do not sustain the Examiner's rejection of claim
11.
In rejecting independent claim 14, the Examiner relies on the
combined findings made in rejecting claims 5 and 11. Final Act. 8. Thus,
because we find the Examiner's rejection of claim 11 is in error, we do not
sustain the Examiner's rejection of independent claim 14. Further, we do
not sustain the Examiner's rejection of claims 15-20, which depend
therefrom.
DECISION
We affirm the Examiner's decision rejecting claims 1-10, 12, and 13.
We reverse the Examiner's decision rejection claims 11 and 14--20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 3 7 C.F .R. § 1.13 6( a )(1 )(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED-IN-PART
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