Ex Parte Mukker et al

Patent Trial and Appeal Board

Jul 29, 2016

13425698 (P.T.A.B. Jul. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/425,698 03/21/2012
57299 7590 08/02/2016
Kathy Manke
A vago Technologies Limited
4380 Ziegler Road
Fort Collins, CO 80525
FIRST NAMED INVENTOR
AtulMukker
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
11-0666 8491
EXAMINER
PORTKA, GARY J
ART UNIT PAPER NUMBER
2138
NOTIFICATION DATE DELIVERY MODE
08/02/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
kathy.manke@broadcom.com
patent.info@broadcom.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte ATUL MUKKER, JAMES A. RIZZO, and
MOBY J. ABRAHAM
Appeal2015-004228
Application 13/425,698 1
Technology Center 2100
Before JEAN R. HOMERE, JOHN F. HORVATH, and
KEVIN C. TROCK, Administrative Patent Judges.
TROCK, Administrative Patent Judge.
DECISION ON APPEAL
Introduction
Appellants seek review under 35 U.S.C. § 134(a) from the
Examiner's Final Rejection of claims 1-18, which constitute all the
claims pending in this application. We have jurisdiction under 35
U.S.C. § 6(b).
We AFFIRM.
1 Appellants indicate the real party in interest is LSI Corporation. App. Br.
3.
Appeal2015-004228
Application 13/425,698
Invention
The claims are directed to rapid offloading of cached data in a
volatile cache memory of a storage controller to a nonvolatile
memory. Abstract.
Exemplary Claim
Exemplary claim 1 is reproduced below:
1. A storage controller comprising:
a cache memory;
control logic coupled with the cache memory and adapted
to couple with one or more storage devices, the control logic
adapted to process I/O write requests received from an attached
host system by storing write data associated with the write I/O
request in the cache memory;
a first flash memory device;
a first communication channel coupling the first flash
device with the control logic;
a second flash memory device; and
a second communication channel coupling the second
flash device with the control logic;
wherein the control logic is further adapted to detect
impending loss of power to the storage controller, wherein the
control logic is further adapted, responsive to detecting the
impending loss of power, to copy a first portion of data in the
cache memory to the first flash memory device through the first
communication channel and to copy a second portion of the write
data in the cache memory to the second flash memory device
through the second communication channel wherein
communications through the first and second communication
channels occur in parallel.
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Application 13/425,698
Rejections
Claims 1, 2, 8-10, 16, and 17 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Andre et al. (US 7, 702,864 B2; Apr. 20, 2010)
("Andre").
Claims 3-5, 11-13, and 18 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Andre and Chatterjee et al. (US 7, 117,310 B2; Oct.
3, 2006) ("Chatterjee").
Claims 6, 7, 14, and 15 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Andre, Chatterjee, and Aloni et al. (US 7,620,057
Bl; Nov. 17, 2009) ("Aloni").
ANALYSIS
We have reviewed the Examiner's rejections and the evidence of
record in light of Appellants' arguments that the Examiner has erred. We
disagree with Appellants' arguments and conclusions. We adopt as our
own: ( 1) the findings and reasons set forth by the Examiner in the action
from which this appeal is taken; and (2) the findings and the reasons set
forth in the Examiner's Answer. We concur with the conclusions reached by
the Examiner and further highlight specific findings and arguments for
emphasis as follows.
Independent Claims 1, 10
Appellants contend the Examiner erred rejecting independent claims 1
and 10 because Andre does not teach or suggest writing to flash memory
devices. App. Br. 7. Appellants argue Andre does not describe either that
the primary logical volumes are flash memory or that they may be
configured in the storage controller. App. Br. 7-8. Appellants assert,
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Application 13/425,698
therefore, that the Examiner's rejection of claim 1 must assume that this
feature is inherent in Andre. App. Br. 8. We disagree.
The Examiner finds, and we agree, Andre teaches that signal-bearing
media may include flash memory and magnetic disks. Ans. 2 (citing Andre
col. 3, 1. 66-col. 4, 1. 7). In Andre, signal-bearing media are described as
storing programs to perform system operations. Id. One of ordinary skill in
the art would have recognized that such programs, like data, must ultimately
be kept on persistent storage in order to prevent their loss during a power
outage. The Examiner reasons, and we agree, that one of ordinary skill in
the art would have recognized directly from the teaching of Andre that such
signal-bearing media could be implemented in flash, and that the persistent
storage media thereof could be implemented in flash. Ans. 3. The Examiner
also finds, and we agree, the implementation of persistent storage as flash
has long been widely recognized in the art as having benefits of faster access
speed and smaller size, as well as being relatively less expensive and more
reliable, in comparison to storage such as magnetic disks. Id.
Accordingly, we are not persuaded the Examiner erred in finding that
Andre teaches or suggests the use of flash memory as described in
independent claims 1 and 10. We, therefore, sustain the Examiner's
rejections of these claims.
Independent Claim 18
Appellants also contend the Examiner erred in rejecting independent
claim 18, because the header buffers of Chatterjee do not correspond
generally to the recited multiple staging buffer memories, and that Chatterjee
does not teach or suggest that its cache lines comprise "a substantially
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Application 13/425,698
similar number of blocks of dirty data, each segment associated with a
corresponding staging buffer memory of the multiple staging buffer
memories," as recited in claim 18. App. Br. 13-14.
The Examiner finds, however, and we agree, that Chatterjee teaches
staging buffers with header blocks, specifically:
[H]eader buffers 208/210, and back-end interface at 110/130
buffer the data to be written to the devices as recited. The use of
buffers in general is widely known in the art to provide
interfacing of different speed devices, without overly burdening
the sending device to match the receiving device speed. Thus it
would have been obvious to one of ordinary skill in the art at the
time of the invention to use staging buffers and store headers
therein, because this was taught in similar caching systems for
nonvolatile storage, and allows for easier interfacing of different
devices.
Ans. 5 (citing Chatterjee, Abstract, Figs. 1-2, col. 5, 11. 31-35, 50-54, col. 8
11. 40-58).
The Examiner also finds, and we agree, that Chatterjee teaches
identification of dirty data, specifically:
The bit which identifies which data is dirty or not, identifies
which data must be flushed to nonvolatile storage. Clearly an
artisan would recognize that one might decide to flush all data,
or only data which is dirty, to avoid having to flush data which
is not necessarily needed (non-dirty data is already stored in
nonvolatile memory). Thus it would have been obvious to one
of ordinary skill in the art at the time of the invention to identify
dirty data, and to perform the dividing, staging and storing of that
data in Andre as recited, because it was known to identify such
dirty data, as an example to avoid flushing data which is already
safely stored in nonvolatile storage.
Ans. 6 (citing Chatterjee Abstract, col. 8, 11. 40-58).
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Accordingly, we are not persuaded the Examiner erred in finding that
the combination of Andre and Chatterjee teaches or suggest the claim
limitations recited in independent 18. We, therefore, sustain the Examiner's
rejections of this claim.
Appellants have not presented separate, substantive, persuasive
arguments with respect to claims 2-9 and 11-17. Therefore, we sustain the
Examiner's rejections of these claims. See 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
We AFFIRM the Examiner's rejections of claims 1-18.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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