Ex Parte Muhammad

Patent Trial and Appeal Board

Nov 25, 2014

12118804 (P.T.A.B. Nov. 25, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte KHURRAM MUHAMMAD
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Appeal 2012-010005
Application 12/118,804
Technology Center 2600
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Before JOSEPH L. DIXON, JAMES R. HUGHES, and
ERIC S. FRAHM, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s final decision rejecting claims 1–4, 6–11, 13–17, and 19. (Br.
2.)1 Claims 5, 12, 18, and 20 are indicated as including allowable subject
matter by the Examiner. (Ans. 3; Br. 2.) We have jurisdiction under 35
U.S.C. § 6(b).
We reverse.

1 We refer to Appellant’s Specification (“Spec.”) filed May 12, 2008 and
Appeal Brief (“Br.”) filed January 4, 2012. We also refer to the Examiner’s
Answer (“Ans.”) mailed March 28, 2012.
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Application 12/118,804

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Appellant’s Invention
The invention at issue on appeal concerns transceivers and methods
for controlling transceiver operation generating interrupts responsive to
setting flags in a flag register and executing an interrupt handling routine
that responds to the interrupts by reloading parameters of the transceiver
and/or generating warnings to downstream components. (Spec. ¶¶ 1, 4–6,
30; Abstract.)
Representative Claim
Independent claim 1, reproduced below with the key disputed
limitations emphasized, further illustrates the invention:
1. A transceiver, comprising:
a processor;
an interrupt system coupled to said processor and having
a flag register associated therewith;
detection circuits associated with corresponding
functional units of said transceiver and configured to detect
conditions regarding said corresponding functional units and set
corresponding flags in said flag register, said interrupt system
configured to assert interrupts in response thereto; and
an interrupt handling routine executable in said
processor and configured to respond to said interrupts by
carrying out at least one of loading parameters and generating
warnings based on identities of said flags.
Rejection on Appeal
The Examiner rejects claims 1–4, 6–11, 13–17, and 19 under 35
U.S.C. § 102(b) as anticipated over US Patent App. Pub. No. 2002/0176390
A1, published Nov. 28, 2002 (“Sparr”).

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Application 12/118,804

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ISSUE
Based upon our review of the administrative record, Appellant’s
contentions, and the Examiner’s findings and conclusions, the pivotal issues
before us follows:
Does the Examiner err in finding that Sparr discloses: (1) a transceiver
including a processor, interrupt system, and interrupt handling routine; and
(2) the “interrupt handling routine . . . respond[ing] to said interrupts by
carrying out at least one of loading parameters and generating warnings
based on identities of said flags” within the meaning of Appellant’s claim 1
and the commensurate limitations of claims 8 and 15?

ANALYSIS
The Examiner rejects independent claim 1 under 35 U.S.C. § 102(b)
as anticipated by Sparr. (Ans. 4–5, 9–14.) Appellant contends, inter alia,
that Sparr does not disclose the disputed features of claim 1. (Br. 6–9.)
Specifically, Appellant contends “Sparr fails to teach a transceiver
comprising a processor” (Br. 8) and Sparr doesn’t disclose an interrupt
handling routine that responds to interrupts by loading parameters or
generating warnings based on the set flags (Br. 8–9).
We agree with Appellant that the portions of Sparr identified by the
Examiner do not disclose the disputed features of independent claim 1, and
we cannot sustain the Examiner’s anticipation rejection for essentially the
reasons set forth by Appellant. (Br. 6–9.)
As pointed out by Appellant (Br. 6–8), claim 1 recites a transceiver
comprising (including) a processor; Sparr describes its processor (Fig. 4,
element 250) as a separate component from its transceiver (Fig. 4, element
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Application 12/118,804

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235). Even if we interpret Sparr’s transceiver and processor as a functional
unit, as urged by the Examiner (Ans. 11–14), Sparr does not necessarily
disclose the processor as part of the transceiver as recited by claim 1.
Additionally, as pointed out by Appellant (Br. 8–9), Sparr does not
describe an interrupt handling routine that responds to interrupts by loading
parameters or generating warnings based on the set flags. The Examiner
does not address loading parameters, and instead focuses on warning
generation. (Ans. 16–17.) Although the Examiner is correct that “[t]he
claim language in no way defines or limits or even suggests the type of
warnings, simply that a warning is generated as a result of the processing
steps . . .” (Ans. 16), we cannot agree that the system operating condition
descriptions (¶ 86) and flag descriptions and/or interrupt descriptions (¶¶ 89,
90) discussed in Sparr in any way describe a warning. (Ans. 16–17). The
descriptions identify system conditions for operating the controller (¶ 86)
(i.e., sent by the processor to the controller) or for which interrupts are
generated (¶¶ 89, 90) (i.e., from the controller to the processor). All
exchange of data between the processor and controller is internal to the
processor/controller functional unit. Nothing in the disclosure of Sparr cited
by the Examiner describes the system handling the generated interrupts by
sending out warnings to downstream components (see Spec. ¶ 30). The
disclosure in Sparr of generating interrupts is simply too tenuous to describe
generating warnings.
Consequently, we are constrained by the record before us to find that
the Examiner erred in finding Sparr discloses the recited features of
Appellant’s claim 1. Appellant’s independent claims 8 and 15 include
limitations of commensurate scope. Appellant’s dependent claims 2–4, 6, 7,
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9–11, 13, 14, 16, 17, and 19 depend on and stand with their respective base
claims. Accordingly, we reverse the Examiner’s anticipation rejection of
claims 1–4, 6–11, 13–17, and 19.

CONCLUSION
Appellant has shown that the Examiner erred in rejecting claims 1–4,
6–11, 13–17, and 19 under 35 U.S.C. § 102(b).

DECISION
We reverse the Examiner’s rejections of claims 1–4, 6–11, 13–17, and
19.

REVERSED

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