Ex Parte Moyer

Patent Trials and Appeals Board

Mar 13, 2019

14504702 - (D) (P.T.A.B. Mar. 13, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/504,702 10/02/2014
34814 7590 03/15/2019
NXP-LARSON NEWMAN, LLP
6501 William Cannon Drive West
Austin, TX 78735
FIRST NAMED INVENTOR
William C. Moyer
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
DN31012NH 8590
EXAMINER
LIN, KATHERINE Y
ART UNIT PAPER NUMBER
2113
NOTIFICATION DATE DELIVERY MODE
03/15/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WILLIAM C. MOYER
Appeal2018-005689
Application 14/504,702 1
Technology Center 2100
Before DAVID M. KOHUT, ERIC B. CHEN, and
JOSEPH P. LENTIVECH, Administrative Patent Judges.
LENTIVECH, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the
Examiner's decision to reject claims 1-20. We have jurisdiction over the
pending claims under 35 U.S.C. § 6(b).
We affirm-in-part.
1 According to Appellant, the real party in interest is "NXP USA, Inc.,
which is a wholly owned subsidiary of Freescale Semiconductor Holdings
V, Inc., which is a wholly owned subsidiary ofNXP B.V., which is a wholly
owned subsidiary ofNXP Semiconductors N.V." App. Br. 2.
Appeal2018-005689
Application 14/504, 702
STATEMENT OF THE CASE
Appellant's Invention
Appellant's invention generally relates to "devices and methods using
electronic devices with watchdog capabilities." Spec. ,r 1. In the invention,
"[ e Jach core of a data processing system can be assigned multiple tasks."
Id. ,r 2. "Each task assigned to a core can be considered an 'active' task."
Id., Abstract. "By knowing that all tasks being monitored are expected to
execute within an expected amount of time, the duration between the strobe
signals [of a watchdog signal] can be set to be longer than that expected
amount of time." Id. "If a task has not transitioned to inactive by a next
strobe, a watchdog error has occurred." Id.
Claims 1, 14, and 19, which are illustrative, read as follows:
1. A method comprising:
in response to a watchdog check signal being asserted at a
first time, storing a first indicator that indicates a state of a first
task of a data processor as active or inactive at the first time;
in response to the watchdog check signal being asserted at
the first time, storing a second indicator that indicates a state of
a second task of the data processor as active or inactive at the
first time;
determining, based on the first and second indicators at a
second time, whether at least one of the first or second task has
been active since the first time; and
in response to determining that at least one of the first or
second task has been active since the first time, asserting an error
indicator.
14. A data processor device comprising:
a task scheduler configured to assign a plurality of tasks to
a corresponding plurality of task identifiers;
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a task state tracker configured to generate a state indicator
for each one of the plurality of tasks that indicates whether a task
is active or inactive;
a watchdog status register having a plurality of storage
locations, each storage location to store a task identifier of a
corresponding one of the plurality of tasks;
a watchdog check circuit configured to generate a
watchdog check signal that is periodically asserted;
watchdog monitor circuit, coupled to the watchdog status
register, to the watchdog check circuit, and to the task state
tracker, that is configured to assert each storage location of the
plurality of storage locations corresponding to a task having an
active state indicator at the time the check signal is asserted, and
to negate each storage location of the plurality of storage
locations corresponding to a task having an inactive state
indicator at the time the check signal is asserted, and
error detect circuitry, coupled the watchdog status register
and to the watchdog check circuit, configured to generate a
watchdog error in response one or more of the plurality of storage
locations being asserted at the time the check signal is asserted.
19. A method comprising:
in response to receiving an asserted watchdog check signal
at a first time, storing a first indicator at a first storage location
that indicates the first task of a data processor is active at the first
time;
receiving a negated watchdog check signal at a second
time that is contiguous to, and after, the first time;
in response to the watchdog check signal being asserted at
a third time that is contiguous to, and after, the second time,
asserting a watchdog error indicator in response to determining
that the first indicator is stored at the first storage location.
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References2
The Examiner relies on the following prior art in rejecting the claims:
Knight
Merrell
US 2014/0082434 Al
us 4,263,647
Rejections
Mar. 20, 2014
Apr. 21, 1981
Claims 1-17, 19, and 20 stand rejected under 35 U.S.C. § 102(a)(l) as
being anticipated by Knight. Final Act. 2-7.
Claim 18 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Knight and Merrell. Final Act. 7-8.
ANALYSIS
Claims 1, 3-6, and 8-13
Generally speaking, illustrative claim 1 requires in disputed part:
storing, at a first time and in response to a watchdog signal, first and second
indicators of whether respective processor tasks are active or inactive at the
first time; and determining, at a second time and based on the stored
indicators, whether either task has been active since the first time.
The Examiner finds claim 1 is anticipated by Knight's teachings
regarding Figures 2A-B and 5A-B. 3 Final Act. 2-3; Ans. 2--4. As to the
disputed claim features, the Examiner finds: Knight's challenge (signals
2 All citations herein to these references are by reference to the first named
inventor only.
3 Knight's Figures 2A-B are directed to monitoring a processor core
("microprocessor"). See, e.g., Knight ,r 20. Knight's Figures 5A-B are
directed to monitoring timers that monitor processor cores. See, e.g., id.
i155.
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Sch) from the watchdog (506) to the timers (502a, b) teaches the claimed
watchdog signal; Knight's responses (signals SRes) from the timers to the
watchdog respectively teach the claimed first and second indicators; and
Knight's timers respectively teach the claimed tasks. Id.
Appellant contends the Examiner erred by finding each of Knight's
responses indicates whether a processor task is active-that is, erred by
finding the responses "indicate[] a ... task of the data processor as active or
inactive at the first time" and are used to "determin[ e] ... [a] task has been
active since the first time" (claim 1). App. Br. 11-12; Reply Br. 3-7.
Specifically, Appellant contends:
[T]he Final Office Action indicates that each internal watchdog
timer ( such as 502a and 502b) represents an active task
(microprocessor) and that the system watchdog timer (506)
monitors all internal watchdog timers. However, an active task
is not the same as a microprocessor. While it is true that the
internal watchdog timers represent corresponding
microprocessors and monitor operations of the microprocessor
(as indicated in the Advisory Action), they do not represent the
actual status of a task of the microprocessor. While a
microprocessor is operating, a particular task, at any time, may
be active or inactive, but system watchdog timer 506 or the
internal timers 502a/502b do not keep track of the active/inactive
status of particular tasks.
App. Br. 12. We are not persuaded.
The Examiner finds the operation of each of Knight's timers teaches a
respective "task of a data processor" ( claim 1 ), because each timer is part of
the microcontroller 500 and its counter value is incremented as part of a
process for monitoring a core of the microcontroller 500. Final Act. 2-3;
Ans. 2-3; see also Knight ,r,r 53-58 (high counter value indicates a core
and/or timer is malfunctioning). Appellant does not rebut this finding with a
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proffered meaning for "task of a data processor" ( claim 1 ), or with sufficient
persuasive evidence of a meaning that distinguishes the claimed tasks over a
timer's monitoring of a core. See In re Jung, 637 F.3d 1356, 1363
(Fed. Cir. 2011) (emphasis added) (describing an appellant's burden to
"articulate what gaps, in fact, exist ... that needed filling by examiner
explanation."); In re Baxter Travenol Labs., 952 F.2d 388, 391
(Fed. Cir. 1991) ("It is not the function of this court to examine the claims in
greater detail than argued by an appellant[.]").
The Examiner further finds, and we agree, each of Knight's responses
includes an estimated counter value of the timer. Final Act. 2-3; Ans. 2-3;
see also Knight ,r,r 20-32 (timer increments the counter value until either:
determining the core is operating properly via the core's correct response to
a challenge; or determining the core is operating improperly via the counter
value exceeding a threshold). As such, the Examiner finds that Knight's
estimated counter values indicate a "task ... as active ... at the first time"
and that the "task has been active since the first time" ( claim 1 ), because an
above-threshold value indicates the timer has continually incremented the
counter (has been "active") since the start of the watchdog period.
Additionally, Appellant contends Knight does not disclose that the
password and estimated counter value are stored in response to the assertion
of a watchdog check signal, as required by claim 1. App. Br. 11, 13.
According to Appellant, Knight discloses that each task sends a
deterministic service request to provide the password and estimated counter
value. App. Br. 11. Appellant argues "there is not a signal in Knight that
operates like the watchdog check signal in which, in response to assertion of
the signal at a first time, an indicator of the status of each of a first and a
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second task as active or inactive is stored." App. Br. 11. Appellant further
argues it is unclear as to whether the Examiner is relying upon Knight's
challenge sent at time tO or the service requests sent at times t2 and t3 but,
regardless of the signal relied upon, Knight does not disclose that the
password and estimated counter value are provided in response to the
assertion of any signal. App. Br. 13.
We find Appellant's arguments unpersuasive because, contrary to
Appellant's above characterization of Knight, Knight's password and
estimated counter value are provided in response to the last challenge.
Knight ,r,r 25-26, 57. Specifically, we agree with the Examiner (Final
Act. 2) that Knight discloses that the deterministic service request is issued
in response to a challenge issued by the system watchdog timer. Knight
Fig. 5B; ,r,r 25, 57. We also agree with the Examiner that Knight further
discloses that the deterministic service request may comprise a register write
and "provides a password and an estimated state variable to the watchdog
timer 202 (e.g., an estimate of the current value of the counter)." Ans. 4;
Knight ,r,r 25, 26. As such, Knight discloses that password and estimated
counter value are stored in response to the issued challenge ( e.g., the
assertion of a watchdog check signal).
Appellant further contends Knight does not disclose:
determining, based on the first and second indicators at a second
time, whether at least one of the first or second task has been
active since the first time; and
in response to determining that at least one of the first or second
task has been active since the first time, asserting an error
indicator,
as recited in claim 1. App. Br. 11-12. Appellant argues:
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Nothing in Knight determines whether at least one of the first or
second task has been active since the first time ( which
corresponds with an assertion of the watchdog timer check
signal). The Final Office Action also cites paragraph 64 of
Knight, but this talks about time allotted for tasks in order to
determine a tolerance value that accounts for the difference in the
actual and estimated counter values. However, in Knight, the
determination of a tolerance, the check of actual counter value,
or the check of a received password against the expected
password is not determining whether at least one of a first task
or a second task has been active since the first time. Also, if the
password or counter value fails comparison in Knight, then the
error is present in Knight. However, claim 1 asserts an error
indicator in response to determining that at least one of the first
or second task has been active since the first time. This is clearly
different from Knight's "error is present" condition described,
for example, in paragraph 26 of Knight.
App. Br. 11-12. Appellant further argues Knight's determination that one of
the password or estimated counter value is not acceptable "does not
specifically indicate that the task has been open since 'the first time."' App.
Br. 13. According to Appellant, "[t]his error indicates simply that there is
not a match but does not indicate that a specific task has been active since
the 'first time."' App. Br. 13. Appellant argues:
[ t ]he error signal in Knight indicates that an error is present in
the microprocessor itself that caused a mismatch of the password
or counter value, but not specifically because a particular task
has been active since assertion of a watchdog check signal. That
is, the error in Knight could have occurred regardless of whether
a particular task is active or inactive.
App. Br. 13 (emphasis omitted).
We find Appellant's arguments unpersuasive because, contrary to
Appellant's above characterization of Knight, Knight's error signal is
generated in response to determining a task has been active. Knight ,r,r 16,
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27. As discussed supra, an above-threshold counter value of a timer
indicates the timer has continually incremented the counter ( that "task has
been active"), since the start of the watchdog period. See supra 7; Knight
,r,r 20-32. Knight further discloses "[i]f the comparison element 210
determines that the expected password or the estimated counter value are
incorrect [e.g., is greater than a threshold value (Knight ,r 16)], an error is
present in the system and an [sic] warning signal is generated to indicate that
an error has occurred in the microprocessor." Knight ,r 27. As such, we
agree with the Examiner that "Knight's determining that the password or
counter values are not acceptable is an error indicator in response to
determining a task has been active since the first time." Ans. 3 (citing
Knight ,r,r 26-27, 32, 57, 64). Accordingly, we are not persuaded the
Examiner erred in finding Knight discloses the disputed limitations.
For the foregoing reasons, we are not persuaded the Examiner erred in
rejecting claim 1; and claims 3---6 and 8-13, which depend from claim 1 and
are not separately argued with particularity. See App. Br. 11-13.
Claim 2
Claim 2 depends from claim 1 and recites "wherein determining
whether at least one of the first or second task has been active since the first
time is in response to the watchdog check signal being asserted at the second
time."
Appellant argues Knight does not disclose the limitations recited in
claim 2. App. Br. 14; Reply Br. 8. In particular, Appellant argues:
[W]hen the error in Knight is determined "at a second time", this
second time does not correspond to a watchdog check signal
being asserted at the second time. That is, if the challenge or
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deterministic service request is provided a second time, a new
password and counter value is provided.
App. Br. 14 (citing Knight ,r,r 26, 27).
We find Appellant's arguments persuasive. At the outset, we note
claim 1 requires that the storing of the indicators occurs in response to the
watchdog check signal at the first time. Claim 2 requires that the consequent
determining of an active task (also recited by claim 1 ), occurs in response to
the watchdog check signal at the second time. Therefore, the Examiner
finds Knight's response including an above-threshold counter value (claimed
indicator of an active task), and the consequently determined error ( claimed
determining), are respectively generated in response to challenges ( claimed
watchdog check signal/s ), asserted at a first time and second time. Final
Act. 2-3; Ans. 5 (citing Knight Figs. 5A, 5B; ,r,r 26-27, 32, 50, 54--55, 57,
64).
However, the Examiner's findings do not explain how Knight's cited
challenges constitute a pair of watchdog check signals as claimed-that is, a
first-time challenge prompting Knight's response including an above-
threshold counter value ( claimed indicator of an active task), and
second-time challenge prompting the consequent determination of error
(claimed determining). See, e.g., Ans. 5. Further, we agree with Appellant
that Knight's Figure 5B shows only a single challenge at the singular time t4
causing an incorrect response (at t5) and consequent error (at t6). Knight
,r,r 56-58. Thus, there are no challenges that respectively prompt a timer's
response including an above-threshold counter value (i.e., an incorrect
response), and the consequent generating of an error.
Accordingly, we do not sustain the rejection of claim 2.
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Claim 7
We agree with the Examiner that Appellant's arguments for claim 7
are merely redundant of the arguments for claim 1. Ans. 5; see also
App. Br. 14; Reply Br. 8. Accordingly, we do not sustain the rejection of
claim 7 for the reasons discussed above with respect to claim 1.
Claims 14-18
Appellant contends Knight fails to disclose a:
watchdog monitor circuit, coupled to the watchdog status
register, to the watchdog check circuit, and to the task state
tracker, that is configured to assert each storage location of the
plurality of storage locations corresponding to a task having an
active state indicator at the time the check signal is asserted, and
to negate each storage location of the plurality of storage
locations corresponding to a task having an inactive state
indicator at the time the check signal is asserted,
as recited in claim 14. App. Br. 14--16; Reply Br. 9-11. Claims 15-18 are
dependent upon claim 14.
The Examiner finds claim 14 is anticipated by Knight's teachings for
Figures 2A-B and 4A-B. Final Act. 5---6; Ans. 6-7. As to the disputed
claim features, the Examiner finds Knight's pin 408 teaches the claimed
watchdog status register. Final Act. 5.
Appellant contends Knight's watchdog pin 408 does not teach
locations that respectively indicate processor tasks as active ( or
inactive). App. Br. 16; Reply Br. 10-11. Specifically, Appellant contends:
"[Knight's] watchdog pin is not a plurality of storage locations which are
asserted or negated when a corresponding task has an active or inactive state
indicator[, but rather] a single output pin that indicates whether the
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microprocessor 404 is operating correctly or not." Reply Br. 10. Appellant
further contends: "FIG. 4A and par. 45--47 of Knight [show] watchdog pin
408 is a single pinout (a single bit) which is toggled between high and low,
and there is only one watchdog pin 408 per microcontroller." Id. at 11.
We find Appellant's arguments persuasive. Generally speaking,
claim 14 requires in disputed part: a watchdog status register having a
storage location for each of multiple processor tasks; asserting a storage
location if a task is active; and negating a storage location if a task is
inactive. The Examiner's findings do not explain how Knight's watchdog
pin 408 teaches a plurality of storage locations for asserting a respective
plurality tasks as active. See, e.g., Ans. 6-7. Further, we agree with
Appellant that Knight's watchdog pin is toggled between "low" and "high"
(Knight ,r,r 4 7, 7 6), which is indicative of a singular bit ( single storage
location). The additional reference, Merrell, is only applied to claim 18 and
is not cited to teach or suggest the disputed limitation. As such, we will not
engage in any inquiry as to whether this additional reference cures the noted
deficiency.
Accordingly, we do not sustain the rejections of claim 14 and its
dependent claims 15-18.
Claims 19 and 20
Appellant contends Knight fails to disclose the limitations recited in
claim 19. App. Br. 16-17; Reply Br. 12. Claim 20 depends upon claim 19.
The Examiner finds claim 19 is anticipated by Knight's teachings for
Figures 2A-B and 4A-B. Final Act. 6-7; Ans. 8. In particular, the
Examiner finds: Knight's watchdog pin 408 (WD pin of Figure 4B), teaches
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the claimed watchdog check signal; Knight's counter value (labeled at to as
Cinit) teaches the claimed indicator; and Knight's times to and t2 respectively
teach the claimed first time ( storing an indicator) and later time ( asserting
the watchdog error if the indicator is stored). Ans. 8 (citing Knight ,r,r 26,
46, 50).
Appellant contends Knight's counter value and watchdog pin 408 do
not respectively teach the claimed indicator and watchdog check signal
because the counter value is not stored in response to the watchdog pin
408. App. Br. 16; Reply Br. 12. Specifically, Appellant contends:
"[Knight's] watchdog pin is also not a watchdog signal which, when
asserted, stores a first indic[a]tor at a first storage location that indicates a
first task of the data processor is active." Reply Br. 12.
We find Appellant's arguments persuasive. Generally speaking,
claim 19 requires: in response to a watchdog check signal at a first time,
storing an indicator at storage location to indicate a task of a data processor
is currently active; and, in response to the watchdog check signal at a later
time ("third time"), asserting a watchdog error if the indicator is stored at the
storage location. The Examiner's findings do not explain how Knight's
counter value ( claimed indicator) is stored in response to setting of the
watchdog pin 408 ( claimed watchdog check signal). See, e.g.,
Ans. 8. Further, we agree with Appellant that Knight, instead, teaches the
watchdog pin 408 as responsive to the counter value, particularly by
describing the pin as responsive to the timer ( 402 ), time checks (TC) of the
counter value, and refresh of the counter value at t0• Knight ,r,r 46-51.
Accordingly, we do not sustain the rejection of claims 19 and its
dependent claim 20.
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DECISION
The Examiner's decision rejecting claims 1 and 3-13 is affirmed.
The Examiner's decision rejecting claims 2 and 14--20 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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