Ex Parte Mouli

Board of Patent Appeals and Interferences

Jan 30, 2009

10680158 (B.P.A.I. Jan. 30, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte CHANDRA MOULI
____________

Appeal 2008-5377
Application 10/680,158
Technology Center 2800
____________

Decided:1 January 30, 2009
____________

Before JOSEPH F. RUGGIERO, JOHN A. JEFFERY,
and MARC S. HOFF, Administrative Patent Judges.

RUGGIERO, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).

Appeal 2008-5377
Application 10/680,158

2
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from the Final Rejection of
claims 1-67. Claims 68-110 have been canceled. We have jurisdiction
under 35 U.S.C. § 6(b).
We affirm.
Appellant’s claimed invention relates to a memory device which
includes a storage transistor having a body portion between first and second
source/drain regions and a gate structure that wraps at least partially around
the body portion in at least two spatial planes. The memory device, which
does not require an additional capacitive storage element, further includes a
bit line connected to the first source/drain region and a word line connected
to the gate structure. (Spec. ¶ [0008]).
Claim 1 is illustrative of the invention and reads as follows:
1. A memory device comprising:
a storage transistor at a surface of a substrate, the storage
transistor comprising:
a body portion between first and second source/drain regions,
wherein the first and second source/drain regions are regions of a first
conductivity type, each of the first and second source/drain regions including
a plurality of layers capable of generating carriers through impact ionization,
and
a gate structure, wherein the gate structure wraps at least
partially around the body portion;
a bit line connected to the first source/drain region; and
a word line connected to the gate structure.

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The Examiner relies on the following prior art references to show
unpatentability:
Takasu US 5,307,305 Apr. 26, 1994
Hu US 5,448,513 Sep. 5, 1995
Yu US 6,221,724 B1 Apr. 24, 2001
Kencke US 6,313,486 B1 Nov. 6, 2001
Matsumoto US 6,806,537 B2 Oct. 19, 2004
(filed Jul. 11, 2002)
Pham US 6,838,322 B2 Jan. 4, 2005
(filed May 1, 2003)

Takashi Ohsawa, Memory Design Using a One-Transistor Gain Cell on SOI,
IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, 1510-22 (November
2002).

Claims 1-7, 11, 12, 17-24, 28-34, 37, 41-53, 56, 57, and 62-67 stand
rejected under 35 U.S.C. § 103(a) as being unpatentable over Ohsawa in
view of Pham and Kencke.2
Claims 8 and 35 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ohsawa, Pham, and Kencke and further in view of Hu.
Claims 14-16, 25, 26, 38-40, and 59-61 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Ohsawa, Pham, and Kencke and
further in view of Matsumoto.3

2 Since the Examiner has treated the limitations of claim 22 in the detailed
analysis of this rejection (Ans. 5), we treat the Examiner’s failure to include
claim 22 in the listing of claims subject to this rejection as harmless
inadvertent error.
3 As with claim 22, the Examiner’s detailed discussion of the limitations of
claims 25 and 26 (Ans. 6), provides an indication that the Examiner
inadvertently failed to include claims 25 and 26 in the listing of claims
subject to this rejection.
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Application 10/680,158

4
Claims 13 and 58 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ohsawa, Pham, and Kencke and further in view of
Takasu.4
Claims 9, 10, 27, 36, 54, and 55 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Ohsawa, Pham, and Kencke and further
in view of Yu.
Rather than reiterate the arguments of Appellant and the Examiner,
reference is made to the Briefs and Answer for the respective details. Only
those arguments actually made by Appellant have been considered in this
decision. Arguments which Appellant could have made but chose not to
make in the Briefs have not been considered and are deemed to be waived
[see 37 C.F.R. § 41.37(c)(1)(vii)].

ISSUE
Under 35 U.S.C. § 103(a), with respect to appealed claims 1-67,
would one of ordinary skill in the art at the time of the invention have found
it obvious to combine Ohsawa with various secondary references to render
the claimed invention unpatentable?

The pivotal issue before us is whether the Examiner erred in
establishing a proper basis for combining the wrap around gate structure
teachings of Pham, as well as the silicon/germanium layer teachings of
Kencke, with the one-transistor memory cell disclosure of Ohsawa.

4 The Examiner’s discussion of the limitations of claim 13 at page 7 of the
Answer is an indication that claim 13 was mistakenly identified as claim
“15” in the Examiner’s listing of claims subject to this rejection.
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FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence:
1. Ohsawa discloses a one-transistor memory cell including an
SOI substrate with opposite conductivity type layers, a partially depleted
storage transistor, first and second source/drain regions, a gate structure
having a gate electrode and a silicon oxide insulating layer, and word and bit
lines connected to, respectively, the gate structure and one of the
source/drain regions. (Ohsawa, Figures 1-3, pages 1510 and 1511).
2. Ohsawa also discloses (page 1510, left column) the design of a
single transistor memory cell which addresses the problems of scalability in
existing DRAM memory cells.
3. Pham discloses the use of double-gated transistors as an
approach to address the scalability problems present in CMOS
semiconductor devices. According to Pham, double-gated transistors
provide for a doubling of the drive current with an inherent coupling
between gates and channel resulting in a more scalable design. (Pham, col.
1, ll. 12-24).
4. Pham also discloses the limitations present in conventional
double-gated MOSFET technology which result in the “inability of these
designs to obtain suitable threshold voltages for high-speed logic devices
while controlling extrinsic resistance.” (Pham, col. 1, ll. 51-54).
5. To address the problems evidenced by existing double-gated
technology, Pham discloses the use of a double-gated MOSFET device,
known as a “FinFET” which takes the form of a gate structure which wraps
around a thin silicon body. According to Pham (col. 2, ll. 57-59), the
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FinFET structure provides “a double gate structure to effectively suppress
short channel effects and enhance drive current.”
6. Pham further discloses (col. 7, ll. 50-65) that FinFET devices
can satisfy many memory integrated circuit requirements and that a
microprocessor memory circuit can include an array of FinFETs over the
logic circuitry of the device.
7. Kencke discloses a field effect transistor which generates
carriers through impact ionization and which uses silicon-germanium
epitaxial layers for better device characteristics as cell size is scaled down.
(Kencke, col. 2, ll. 45-61 and col. 4, ll. 1-14).
8. Hu discloses a capacitor-less DRAM device (col. 4, ll. 50-53) in
which the use of heavily doped regions of a second conductivity type
adjacent to a source/drain region and separated from the other source/drain
region results in the use of less voltage during write operations.
9. Matsumoto discloses (Figure 25, col. 17, ll. 56-60) a
semiconductor device which uses silicidation techniques to reduce the gain
of parasitic bipolar transistors.
10. Takasu discloses (Figure 1, col. 17, ll. 56-60) a semiconductor
device which uses insulating material with a high dielectric constant to
“obtain good FET characteristics.”
11. Yu discloses (Figure 1, col. 2, ll. 1-2) an integrated circuit
device in which inert dopants are used to suppress punch-through effects
between device regions.

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PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). In so
doing, the Examiner must make the factual determinations set forth in
Graham v. John Deere Co., 383 U.S. 1, 17 (1966). “[T]he examiner bears
the initial burden, on review of the prior art or on any other ground, of
presenting a prima facie case of unpatentability.” In re Oetiker, 977 F.2d
1443, 1445 (Fed. Cir. 1992). Furthermore,
“‘there must be some articulated reasoning with some
rational underpinning to support the legal conclusion of
obviousness’ . . . [H]owever, the analysis need not seek out
precise teachings directed to the specific subject matter of the
challenged claim, for a court can take account of the inferences
and creative steps that a person of ordinary skill in the art
would employ.”

KSR Int’l Co. v. Teleflex Inc., 127 S. Ct. 1727, 1741 (2007) (quoting
In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).
Also, “[t]he combination of familiar elements according to known
methods is likely to be obvious when it does no more than yield predictable
results.” Leapfrog Enter., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1161
(Fed. Cir. 2007) (quoting KSR, 127 S. Ct. at 1739). “One of the ways in
which a patent's subject matter can be proved obvious is by noting that there
existed at the time of invention a known problem for which there was an
obvious solution encompassed by the patent’s claims.” KSR, 127 S. Ct. at
1742.

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ANALYSIS
I. The rejection of claims 1-7, 11, 12, 17-24, 28-34, 37, 41-53, 56,
57, and 62-67 based on the combination of Ohsawa, Pham, and
Kencke.

With respect to the 35 U.S.C. § 103(a) rejection of independent claims
1, 23, 28, 30, 32, and 47 based on the combination of Ohsawa, Pham, and
Kencke, Appellant’s arguments in response assert a failure by the Examiner
to establish a prima facie case of obviousness since a proper basis for the
Examiner’s proposed combination of references has not been established.
According to Appellant (App. Br. 9 and 11; Reply Br. 6), the Pham
reference, relied upon by the Examiner for the disclosure of a transistor with
a wrap around gate structure, has no storage transistor teaching or suggestion
related to the described FinFET transistor structure that would have any
application to the disclosed one transistor memory device of Ohsawa.
We do not agree with Appellant. Appellant’s arguments to the
contrary notwithstanding, Pham discloses the application of the disclosed
FinFET structure, which includes a wrap around gate feature, to memory
circuits for microprocessor applications. As suggested by Pham (col. 7, ll.
50-65, Figure 12), microprocessor memory circuits may include an array of
multi-layer polysilicon FinFETs 90 over logic circuitry on a device
insulative layer 86.
We further find Appellant’s arguments that the disclosure of Pham
“teaches away” from any combination with Ohsawa to be unpersuasive. In
making this argument, Appellant focus on the alleged unsuitability of
Pham’s disclosed FinFET transistor structure to be used as a storage
transistor such as in the device of Ohsawa. To support this contention,
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Appellant calls attention (App. Br. 12-15; Reply Br. 7-10) to Pham’s
absence of any disclosure of channel doping. According to Appellant (id.),
storage transistors, such as disclosed by Ohsawa, make use of a floating
body effect which requires channel doping, a feature which Pham does not
use and which is suggested by Pham to be undesirable. Appellant expands
upon the “teaches away” argument (Reply Br. 10) by calling attention to
Ohsawa’s use of “polysilicon pillars” as stabilizing capacitors which, in
Appellant’s view, would be incompatible with Pham’s wrap around gate
structure teachings.5
Initially, however, it is apparent to us from the Examiner’s stated
position (Ans. 4, 9, and 10) that the Examiner is not suggesting the bodily
incorporation of the FinFET transistor structure of Pham into the memory
cell device of Ohsawa. Rather, it is Pham’s teaching (col. 1, ll. 51-54 and
col. 2, ll. 57-59) of using a wrap around gate structure to address the
problem of achieving proper threshold voltages while controlling extrinsic
resistance and enhancing drive current in planar devices that is relied on as a
rationale for the proposed combination with Ohsawa’s memory cell
disclosure. “The test for obviousness is not whether the features of a
secondary reference may be bodily incorporated into the structure of the
primary reference.... Rather, the test is what the combined teachings of those
references would have suggested to those of ordinary skill in the art.” See In
re Keller, 642 F.2d 414, 425 (CCPA 1981) and In re Nievelt, 482 F.2d 965,
968 (CCPA 1973).

5 We do not find the reproduced Figure 9.1.1(c) and (d) illustrations, nor do
we find the page numbers referenced by Appellant (Reply Br. 10), in the
Ohsawa reference cited and applied by the Examiner.
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We further find to be unpersuasive Appellant’s argument that Pham’s
FinFET transistor device does not include channel doping and, therefore,
“teaches away” from use as a storage transistor which would require channel
doping to achieve the necessary floating body effect. We agree with the
Examiner (Ans. 8-9) that Appellant’s channel doping argument
mischaracterizes the disclosure of Pham since it is only “intense” channel
doping that Pham suggests as a feature to be avoided. (Pham, col. 1, ll. 33-
35). Further, we find that any aversion to intense channel doping that may
be present in the disclosure of Pham does not “teach away” from a
combination with Ohsawa since, as pointed out by the Examiner (id., at 9),
there is no indication that the device of Ohsawa (e.g., Figure 3) includes
intense or highly doped channels.
We further find no error in the Examiner’s articulated line of
reasoning (Ans. 5 and 9) which provides a basis for the conclusion that the
wrap around gate structure teachings of Pham would have served as an
obvious enhancement to the memory structure disclosed by Ohsawa. We
find that Pham addresses (col. 1, ll. 12-35) a scalability problem existent in
CMOS semiconductor devices, a problem which is also discussed by
Ohsawa at the left column of page 1510. In our view, the ordinarily skilled
artisan in seeking solutions to the known scalability problems in DRAM
memory cells would have found of interest Pham’s teachings of double-gate
structures and, particularly, Pham’s wrap around gate structure improvement
on existing double gate structure technology (Pham, col. 1, ll. 51-54 and col.
2, ll. 57-59). According to Leapfrog, when a combination of familiar
elements according to methods known to the skilled artisan achieves a
predictable result, it is likely to be obvious.
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Lastly, we find no error in the Examiner’s application of the silicon-
germanium layer and impact ionization teachings of Kencke to the device of
Ohsawa as modified by Pham. Appellant’s arguments (App. Br. 15 and 16;
Reply Br. 12) to the contrary notwithstanding, the Examiner’s articulated
line of reasoning (Ans. 5, 10, and 11) that the use of silicon-germanium
epitaxial layers and impact ionization improves device characteristics is
directly supported by the disclosure of Kencke (col. 4, ll. 1-5). Of further
significance, Kencke notes (id.) an improvement in device characteristics as
cell size scales down, a problem of concern to both Ohsawa and Pham as
discussed supra.
For the above reasons, since it is our opinion that the Examiner has
established a prima facie case of obviousness which has not been overcome
by any convincing arguments from Appellant, the Examiner’s 35 U.S.C.
§ 103(a) rejection of independent claims 1, 23, 28, 30, 32, and 47, as well as
dependent claims 2-7, 11, 12, 17-24, 29, 31, 33, 34, 37, 41-46, 48-53, 56, 57,
and 62-67 not separately argued by Appellant, is sustained.

II. The rejection of dependent claims 8 and 35 based on the
combination of Ohsawa, Pham, Kencke, and Hu.

The Examiner’s obviousness rejection of dependent claims 8 and 35 is
also sustained. We find no error in the Examiner’s line of reasoning (Ans. 5,
6, and 11) establishing the obviousness to the ordinarily skilled artisan of
applying the heavily doped region teachings of Hu to the combination of
Ohsawa, Pham, and Kencke. As with the previously discussed rejection, we
do not interpret the Examiner’s position as suggesting the bodily
incorporation of Hu’s DRAM device structure into the memory cell device
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of Ohsawa. Rather, it is Hu’s teaching (col. 4, ll. 50-53) of using heavily
doped regions of a second conductivity type adjacent to a source/drain
region and separated from the other source/drain region resulting in the use
of less voltage during write operations that is relied on as a rationale for the
proposed combination with Ohsawa’s memory cell disclosure.

III. The rejection of dependent claims 14-16, 25, 26, 38-40, and
59-61 based on the combination of Ohsawa, Pham, Kencke,
and Matsumoto.

This rejection is sustained as well. We find no error in the Examiner’s
application (Ans. 6) of the silicidation teachings of Matsumoto (Figure 25,
col. 17, ll. 56-60) to the device of Ohsawa as modified by Pham and Kencke.
Appellant’s arguments (App. Br. 17) rely on the arguments asserted
previously against independent claims 1, 32, and 47, which arguments we
found to be unpersuasive for all of the previously discussed reasons.

IV. The rejection of dependent claims 13 and 58 based on the
combination of Ohsawa, Pham, Kencke, and Takasu.

In addressing the language of dependent claims 13 and 58, the
Examiner has applied (Ans. 7) the high dielectric constant insulating
material teachings of Takasu to the combination of Ohsawa, Pham, and
Kencke. Appellant’s arguments (App. Br. 17), which rely on previously
asserted unpersuasive arguments made against independent claims 1 and 47,
are not convincing of any error in the Examiner’s position. Accordingly, the
Examiner’s obviousness rejection of dependent claims 13 and 58 is
sustained.
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V. The rejection of dependent claims 9, 10, 27, 36, 54, and 55
based on the combination of Ohsawa, Pham, Kencke, and Yu.

This rejection is also sustained. We also find no error in the
Examiner’s application of the inert dopant teachings of Yu to the
combination of Ohsawa, Pham, and Kencke. Appellant’s arguments (App.
Br. 17 and 18) again rely on arguments made against the rejection of
independent claims 1, 23, 32, and 47, which arguments we found to be
unpersuasive as previously discussed.

CONCLUSION OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellant has not shown that the Examiner erred in rejecting claims 1-67 for
obviousness under 35 U.S.C. § 103.

DECISION
The Examiner’s 35 U.S.C. § 103 rejection of claims 1-67, all of the
appealed claims, is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

KIS

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