Ex Parte Moskovich et al

Patent Trial and Appeal Board

Mar 14, 2018

13979859 (P.T.A.B. Mar. 14, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/979,859 07/16/2013 Ilia Moskovich NM45950EH 5228
23125 7590 03/16/2018
NXP USA, Inc.
LAW DEPARTMENT
6501 William Cannon Drive West TX30/OE62
AUSTIN, TX 78735
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
03/16/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ILIA MOSKOVICH, ROY GLASNER, and
DMITRY LACHOVER
Appeal 2017-008784
Application 13/979,859
Technology Center 2100
Before JUSTIN BUSCH, NORMAN H. BEAMER and
SCOTT B. HOWARD, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellants appeal from the
Examiner’s decision to reject claims 1, 2, and 6—14, which constitute all the
claims pending in this application. We have jurisdiction over the pending
claims under 35 U.S.C. § 6(b). Claims 3—5 and 15 were cancelled
previously. We reverse.
CLAIMED SUBJECT MATTER
Appellants’ “invention relates to a device and a method for computing
a function value of a function as described in the accompanying claims.”
Spec. 1. More specifically, Appellants’ invention is directed to evaluating
an approximation function rather than a more complex function to more
Appeal 2017-008784
Application 13/979,859
quickly determine the result for a given input value. Id. at 4. A claimed
aspects of Appellants’ invention includes a memory storing a look-up table
including numbers in fixed-point formats and a converter for converting
fixed-point numbers to floating-point numbers. Id. at 7. Claim 1 is the only
independent claim. Claim 1 is illustrative and reproduced below:
1. A device for computing a function value of a function F,
comprising:
a memory storing a look-up table comprising a first set of
entries storing numbers in a first fixed-point format and a second
set of entries storing numbers in a second fixed-point format,
each entry of the first and second set of entries of which entries
having associated with a corresponding domain and a
corresponding approximation function for approximating the
function F on the associated domain;
a truncator unit arranged to truncate or round a first value
XI to generate a second value X2;
a selector unit, coupled to the truncator unit and the
memory, and arranged to select an entry of the look-up table
according to the second value X2, thus selecting the
approximation function that is associated with the selected entry;
a first fixed-point to floating-point converter comprising a
first register, a second register, and a first multiplexer, the first
register and the second register coupled to the first multiplexer
and the first multiplexer configured to select contents of the first
or second register, wherein the first register stores a first
representation of a first set number of the first set of entries, the
first or second registers to output a floating-point representation
of the first set number based on one or more of an index of the
first set of entries or a characteristic of the first set number;
a second fixed-point to floating-point converter
comprising a third register, a fourth register, and a second
multiplexer, the third register and the fourth register coupled to
the second multiplexer and the second multiplexer configured to
select contents of the third or fourth register, wherein the third
register stores a first representation of a second set number of the
second set of entries, the fourth register stores a second
2
Appeal 2017-008784
Application 13/979,859
representation of the second set number of the second set of
entries, and the second multiplexer is configured to select one of
the third or fourth registers to output a floating-point
representation of the second set number based on one or more of
an index of the second set of entries or a characteristic of the
second set number; and
an evaluator unit, coupled to the selector unit, and
arranged to determine the function value of the selected
approximation function at the first value XL
REJECTIONS
Claims 1, 2 and 7—14 stand rejected under AIA 35 U.S.C. § 103(a) as
obvious in view of Hussain (US 2007/0061389 Al; Mar. 15, 2007) and Kato
(US 2009/0113186 Al; Apr. 30, 2009). Final Act. 6-13.
Claim 6 stands rejected under AIA 35 U.S.C. § 103(a) as obvious in
view of Hussain, Kato, and Endo (US 2005/0160129 Al; July 21, 2005).
Final Act. 14.
ANALYSIS
The Examiner rejects claims 1, 2, and 7—14 as obvious in view of
Hussain and Kato and claim 6 as obvious in view of Hussain, Kato, and
Endo. Final Act. 6—14. Of particular note, with respect to claim 1, the
Examiner finds Hussain teaches or suggests “a memory storing a look-up
table comprising a first set of entries storing numbers in a first fixed-point
format and a second set of entries storing numbers in a second fixed-point
format.” Final Act. 6.
The Examiner finds Hussain’s disclosure of tables storing elements of
Taylor series number approximations in 16-bit and 10-bit compressed non-
IEEE 754 format teaches or suggests storing numbers in two fixed-point
formats and “the first and second converters as cited above and depicted in
the embodiment of FIG. 8, when combined with the embodiment of FIG. 4,
3
Appeal 2017-008784
Application 13/979,859
. . . convert the fixed-point numbers in the look-up table into floating-point
numbers.” Final Act. 15 (citing Hussain 140, Figs. 4, 8). The Examiner
further finds Hussain discloses storing values in a compressed format in
tables 1 and 2, and Hussain defines compressed as “a ‘storage state wherein
only a portion [. . .] of the mantissa of the value’ is stored.” Ans. 2 (brackets
in original) (citing Hussain || 40-41, Fig. 7). The Examiner explains that
numbers stored in floating-point format include three components: a sign,
an exponent, and a mantissa. Id. at 2—3. Thus, because Hussain stores
values in tables 1 and 2 in a compressed format, which “is a portion of a
fixed[-]point value,” those values are stored in fixed-point format. Id. at 3.
Appellants contend Hussain does not teach or suggest fixed-point
formatted numbers because the numbers discussed in Hussain’s paragraphs
40 through 42 and depicted in Figure 4 have exponents. App. Br. 7.
Appellants further assert Hussain’s disclosure of compressed non-IEEE 754
compliant numbers may include floating-point formatted numbers that do
not comply with IEEE 754. Id. Appellants argue Hussain’s disclosure that
inputs do not need to be normalized numbers if the floating point unit (FPU)
is IEEE 754 compliant does not mean the inputs are fixed-point, but simply
implies the inputs are not normalized if the FPU is non-IEEE 754 compliant
as opposed to the Examiner’s finding that the inputs. Id. Appellants argue,
contrary to the Examiner’s finding, the mantissa of a floating-point format
number is not a separate fixed-point format number. Reply Br. 3.
Hussain discloses logarithm processing systems and methods having
“two tables corresponding to various base and derivative functions of a
logarithm, with logic configured to access the tables and format and
normalize the accessed values to evaluate the logarithm using a standard
4
Appeal 2017-008784
Application 13/979,859
FMAD [(fused multiply-and-add operation)] unit.” Hussain, Abstract.
More specifically, Hussain is directed to reducing dedicated logic for
logarithmic evaluation by using existing FMAD hardware by implementing
logarithmic instruction sets “that include ‘primitive’ operations which may
be supported in standard FMAD hardware.” Id. 120. “FMAD hardware is
exploited by normalizing and full-precision formatting the inputs and
configuring the floating point numbers in standardized format, such as
IEEE-754 format.” Id. Inputs to IEEE 754 compliant floating point units
are normalized numbers. Id. 132.
Because the utilized range of values for the first and second derivative
functions is limited, Hussain is able to store values in its table 1/2 (element
318) and the destination register (element 322, used for storing the results of
the look-up) “in a compressed non-single precision (non-IEEE-754) format.”
Id. 140. Hussain discloses that “functions corresponding to table 1/2 318
can be stored in a normalized format, non-single precision format (non-
IEEE-754).” Id. 141 (formatting added). Hussain further explains the
values can be stored in a compressed format, wherein “compressed refers to
the storage state wherein only a portion ... of the mantissa of the value . . .
and a bit to indicate whether the exponent is 1 or 0 is stored in a normalized
format,” which obviates the need to store the first derivative value in full
precision, IEEE 754 format. Id. Hussain discloses the second derivative
function may also be stored in a compressed format. Id. 142. Hussain’s
formatters then uncompress the compressed non-IEEE 754 format values
stored in the destination register (element 322) and transform the
uncompressed numbers into single precision IEEE 754 format. Id. 145.
5
Appeal 2017-008784
Application 13/979,859
We agree with Appellants. Hussain does not mention fixed-point
format numbers and the Examiner’s explanation fails to clearly demonstrate
that Hussain’s compressed non-IEEE 754 numbers teach or suggest fixed-
point format numbers. There is no dispute that floating point numbers are
made up of a sign, an exponent, and a mantissa. See Ans. 2—3; Reply Br. 3.
We agree with Appellants that Hussain’s disclosure of non-IEEE 754
compliant numbers does not suggest that the numbers are stored in fixed-
point format.
Moreover, we disagree with the Examiner’s finding that Hussain’s
disclosure of storing only a portion of the mantissa suggests a fixed-point
format value. See Ans. 3. First, Hussain disclosing storing the compressed
numbers in a register but indicates the numbers are still associated with an
exponent and sign, such that the true value of the stored number cannot be
determined without interpreting the stored value as a floating-point format
number. Second, Hussain states that the portion of the mantissa of the value
“and a bit to indicate whether the exponent is 1 or 0 is stored.” Hussain
141. We read that disclosure in Hussain as indicating that the register stores
a bit representing the exponent, which is necessary to evaluate the actual
value stored. Thus, we understand the value in the register to be a floating­
point format number.
Constrained by this record, and for the reasons discussed above, we
are persuaded the Examiner erred in finding Hussain teaches or suggests “a
memory storing a look-up table comprising a first set of entries storing
numbers in a first fixed-point format and a second set of entries storing
numbers in a second fixed-point format,” as recited in claim 1. Accordingly,
we do not sustain the Examiner’s rejection of independent claim 1. For
6
Appeal 2017-008784
Application 13/979,859
similar reasons, we also do not sustain the Examiner’s rejections of claims 2
and 6—14, which depend therefrom.
DECISION
We reverse the Examiner’s decision to reject claims 1, 2, and 6—14
under 35 U.S.C. § 103(a).
REVERSED
7