Ex Parte Morad et al

Patent Trial and Appeal Board

Jul 17, 2014

10887950 (P.T.A.B. Jul. 17, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/887,950 07/09/2004 Amir Morad 106861-0589 5216
121312 7590 07/18/2014
Foley & Lardner LLP/ Broadcom Corporation
3000 K Street N.W, Suite 600
Washington, DC 20007-5109
EXAMINER
DIEP, NHON THANH
ART UNIT PAPER NUMBER
2487
MAIL DATE DELIVERY MODE
07/18/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte AMIR MORAD and LEONID YAVITS
____________________

Appeal 2011-0128851
Application 10/887,950
Technology Center 2400
____________________

Before JEAN R. HOMERE, CARL W. WHITEHEAD JR., and
CATHERINE SHIANG, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is Broadcom Corporation. App. Br. 1.
Appeal 2011-012885
Application 10/887,950

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) (2002) from the
Examiner’s Final Rejection of claims 32–35 and 37–41. Claims 1–31 and
36 have been canceled. App. Br. 2. We have jurisdiction under 35 U.S.C.
§ 6(b) (2008).
We affirm.
Appellants’ Invention
Appellants invented a motion estimating processor (108) for
performing motion analysis of various image resolutions of a digital video
signal. In particular, the motion estimating processor (108) includes a low
resolution processor (150), a full resolution processor (152) and a high
resolution processor (154) for performing motion analysis on corresponding
image resolution portions of the digital video signal. Fig. 3, Spec. 15, ll. 14-
18.
Illustrative Claim
Independent claim 32 further illustrates the invention. It reads as
follows:
32. A motion estimation device comprising:
a full resolution processor operable to perform motion analysis
upon a digital video signal; and
a high resolution processor operable to perform motion analysis
upon the digital
video signal at an increased image resolution that is greater than
full resolution.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Appeal 2011-012885
Application 10/887,950

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Gonzales US 5,414,469 May 9, 1995
Uchida US 5,610,658 Mar. 11, 1997

Rejection on Appeal
The Examiner rejects claims 32–35 and 37–41 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Uchida and
Gonzales.

ANALYSIS
We consider Appellants’ arguments seriatim as they are presented in
the Appeal Brief, pages 4-8, and the Reply Brief, pages 4-9.2
Dispositive Issue: Under 35 U.S.C. § 103, did the Examiner err in
finding the combination of Uchida and Gonzales teaches or suggests a
motion estimation processor including a full resolution processor and a high
resolution processor, as recited in claim 32?
Appellants argue that the proposed combination of Uchida and
Gonzales does not teach or suggest the disputed limitations emphasized
above. Id. According to Appellants, Uchida discloses a single processor
(108) including a first, a second, and a third hierarchy amount of movement
circuits (18, 16, and 14) for detecting movement in a digital signal.
Appellants argue, however, while the first amount of movement circuit (18)

2 Rather than reiterate the arguments of Appellants and the Examiner, we
refer to the Appeal Brief (filed February 28, 2011), the Reply Brief (filed
July 26, 2011) and the Answer (mailed May 26, 2011) for the respective
details. We have considered in this decision only those arguments
Appellants actually raised in the Briefs. Any other arguments Appellants
could have made but chose not to make in the Briefs are deemed to be
waived. See 37 C.F.R. § 41.37(c)(1)(vii).
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Application 10/887,950

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performs full resolution detection, the second and third circuits (16 and 14)
only perform reduced resolution detection. That is, none of the disclosed
circuits teaches a high resolution processor that performs motion analysis
upon the digital video signal at an increased image resolution greater than
full resolution. App. Br. 5–7, Reply Br. 6–8. Further, Appellants argue
because Gonzales’ disclosure of scaling macroblocks to a resolution higher
than the full resolution does not teach performing motion analysis at such
higher resolution, it does not cure the noted deficiencies of Uchida. App. Br.
8–9, Reply Br. 7–8.
In response, the Examiner finds that while Uchida discloses a first
hierarchy circuit for performing full resolution detection, a second and third
hierarchy circuit for performing reduced resolution detections, the disclosed
circuits teach a plurality of resolution processors contained in the amount of
movement detection device of Figure 1. Ans. 9–10. Further, the Examiner
finds Gonzales’ disclosure of a circuit for scaling a macroblock to a
resolution higher than a full resolution teaches the high resolution processor.
Id. at 13.
On the record before us, we find no error in the Examiner’s
obviousness rejection of claim 32. In particular, we find because the amount
of hierarchy movement detection circuits disclosed in Uchida are capable of
performing processing functions such as obtaining image movement data
from memory, transforming the obtained data, and transmitting the
transformed data to another circuit (col. 3, l. 65–col. 4, l. 64), such
processing functions performed by those hierarchy circuits qualify them to
teach the claimed processors. Next, we find that Gonzales’ disclosure of a
circuit for scaling macroblocks to an image resolution greater than full
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Application 10/887,950

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resolution (col. 8, ll. 61-63) would complement Uchida’s system by allowing
it to process a high resolution image thereby performing motion analysis
upon the video signal at high resolution. Because we are satisfied that
Uchida and Gonzales disclose prior art elements that perform their ordinary
functions to predictably result in the disputed limitations, Appellants have
therefore not shown error in the Examiner’s rejection of claim 32.
Because Appellants have not provided separate argument against the
rejection of claims 33–35 and 37–41, these claims fall with claim 32 for
same reasons set forth above. See 37 C.F.R. § 41.37(c)(1)(vii).

DECISION
We affirm the Examiner’s rejections of claims 32–35 and 37–41 as set
forth above.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

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