Ex Parte Mody

Patent Trial and Appeal Board

Oct 30, 2018

13769480 (P.T.A.B. Oct. 30, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/769,480 02/18/2013
23494 7590 11/01/2018
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
UNITED ST A TES OF AMERICA
FIRST NAMED INVENTOR
Mihir N arendra Mody
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-71067 8547
EXAMINER
JOISIL, BERTEAU
ART UNIT PAPER NUMBER
2487
NOTIFICATION DATE DELIVERY MODE
11/01/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MIHIR NARENDRA MODY
Appeal2018-004356
Application 13/769,480
Technology Center 2400
Before LARRY J. HUME, JENNIFER L. McKEOWN, and
MATTHEW J. McNEILL, Administrative Patent Judges.
McKEOWN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner's
decision to reject claims 1 and 17. Claims 2-16 and 18-20 have been
cancelled.
We reverse.
1 According to Appellant, the real party in interest is Texas Instruments
Incorporated. App. Br. 2.
Appeal2018-004356
Application 13/769,480
STATEMENT OF THE CASE
Appellant's disclosed and claimed invention is directed to "[s]everal
systems and methods for processing of video frames based on one or more
video formats." Abstract. For example,
In an embodiment, a video processing system comprises a
memory and a video engine. The memory stores a plurality of
video frames, a primary set of instructions and a plurality of
secondary sets of processing instructions. Each secondary set of
processing instructions is associated with a video format. The
video engine is loaded with the primary set of instructions and is
configured to fetch one or more video frames and a secondary set
of processing instructions from the memory based on the loaded
primary set of instructions. The fetched secondary set of
processing instructions corresponds to a video format determined
for processing of the one or more video frames. The video engine
performs processing of the one or more video frames based on
the secondary set of processing instructions.
Abstract.
Claim 1 is illustrative of the claimed invention and reads as follows:
1. A video processing system, comprising:
a memory configured to store a plurality of video frames,
a primary set of instructions and a plurality of secondary sets of
processing instructions, wherein each of the secondary sets of
processing instructions is associated with a respective one of a
plurality of video formats; and
a video engine communicatively coupled to the memory,
the video engine including a processing module, a memory
module and a direct memory access (DMA) module, the memory
module configured to be loaded with the primary set of
instructions from the memory, the processing module configured
to:
access the primary set of instructions from the memory
module;
program the DMA module to load a secondary set of
processing instructions of the secondary sets of processing
instructions based on the primary set of instructions;
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Application 13/769,480
sleep upon programming the DMA module to load the
secondary set of processing instructions, the DMA module being
configured to load the secondary set of processing instructions
while the processing module is sleeping and interrupt the
processing module upon completion of loading the secondary set
of processing instructions;
wake up from the sleep in response to receiving an
interrupt from the DMA module; and
perform processing of one or more video frames based on
the secondary set of processing instructions.
THE REJECTION
The Examiner rejected claims 1 and 172 under 35 U.S.C. § 103 as
unpatentable over Azar (US 2007/0103590 Al; pub. May 10, 2007), Sha
(US 8,127,058 Bl; issued Feb. 28, 2012), and Bougard (US 2009/0175381
Al; pub. July 9, 2009). Final Act. 5-14.
ANALYSIS
THE REJECTION UNDER 35 U.S.C. § 103 BASED ON AZAR, SHA, AND BOUGARD
Claims 1 and 17
Based on the record before us, we are persuaded that the Examiner
erred in rejecting claims 1 and 17 as unpatentable over Azar and Spa.
Appellant asserts that neither Azar nor Sha describe programing the
direct access memory ("DMA") module to load a secondary set of
processing instructions based on a primary set of instructions. Reply Br. 4;
App. Br. 5-7. For example, Appellant contends:
Claim 1 further limits the video engine to program a DMA
module to load a secondary set of processing instructions based
on a primary set of instructions.
2 The Final Action includes claims 2-16 and 18-20, but the Appellant has
since cancelled these claims and, thus, only claims 1 and 17 remain rejected.
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Application 13/769,480
A person of ordinary skill in the art, upon reading the
applied references, learns to receive video data into a frame
buffer of the master GPU using a DMA, use a host controller to
initiate a DMA command, and to use two single-port direct
memory access controllers (DMAC) with an adjustable FIFO
depth.
No person of ordinary skill in this art, upon reading the
applied references, could have learned of a video engine that
programs a DMA module, as recited in claim 1, much less a
video engine that programs a DMA module to load a secondary
set of processing instructions based on a primary set of
instructions. Accordingly, the applied references fail to render
obvious the invention defined by Appellant's claim 1.
App. Br. 7. Appellant also argues it is unclear which reference or
combination of references the Examiner relies on as teaching this limitation.
App. Br. 7.
The Examiner acknowledges that Azar does not teach programing the
DMA module to load a secondary set of processing instructions based on a
primary set of instructions (Final Act. 6) and appears to rely on Sha for this
disputed limitation. Namely, the Examiner finds:
Sha can be interpreted to disclose the video engine configured to
fetch one or more video frames from among the plurality of video
frames and a secondary set of processing instructions from
among the plurality of secondary sets of processing instructions
from the memory based on the loaded primary set of instructions.
Final Act. 6; Ans. 5. As support, the Examiner solely cites Sha's col. 22,
11. 19-28, which teaches configuration data of two types including a lookup
table. Final Act. 6; Ans. 5. The Examiner also finds Azur discloses a GPU
memory which is configured to store of GPU instructions. Final Act. 5.
While we recognize that Sha teaches a video processor that supports a
plurality of video formats (see, e.g., Sha col. 4, 11. 16-25) and a look up table
of configuration data (Final Act. 6-7 citing Sha col. 22, 11. 19-28), it is
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Application 13/769,480
unclear how Sha teaches programming the DMA module to load a secondary
set of processing instructions based on the primary set of instructions.
Notably absent is any explanation or reasoning as to how Azar's teaching of
generally storing GPU instructions to process video frames and Sha' s
teaching of a look up table for configuration data would teach or suggesting
programming the DMA module to load one set of instructions based on
another set of instructions.
Appellant's also challenge the Examiner's reliance on Bougard as
teaching sleeping upon programming the DMA module to load the
secondary set of processing instructions. See, e.g. Reply Br. 3; see also
Final Act. 7 (citing Bougard paragraphs ,r,r 83 and 88 as support). While
Bougard generally teaches a sleep mode (Bougard ,r 86) that can be set when
no signal is detected (Bougard ,r 92) and also teaches a wake up upon
completion of a data transfer (Bougard ,r 92), it is unclear how these
teachings render obvious the limitation of a processing module configured to
sleep upon programming the DMA module to load the secondary set of
processing instructions.
So in order for us to sustain the Examiner's rejection, we would need
to resort to impermissible speculation or unfounded assumptions or
rationales to supply deficiencies in the factual bases of the rejection before
us. In re Warner, 379 F.2d 1011, 1017 (CCPA 1967). Accordingly, based
on the record before us, we reverse the Examiner's rejection of claims 1 and
17 as unpatentable over Azar, Sha, and Bougard.
DECISION
We reverse the Examiner's decision to reject claims 1 and 17.
REVERSED
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