Ex Parte Miyazaki

Patent Trial and Appeal Board

Mar 31, 2015

11652977 (P.T.A.B. Mar. 31, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/652,977 01/10/2007 Aya Miyazaki 0553-0563 5812
24628 7590 03/31/2015
Husch Blackwell LLP
Husch Blackwell Sanders LLP Welsh & Katz
120 S RIVERSIDE PLAZA
22ND FLOOR
CHICAGO, IL 60606
EXAMINER
TUNG, DAVID
ART UNIT PAPER NUMBER
2694
MAIL DATE DELIVERY MODE
03/31/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte AYA MIYAZAKI
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Appeal 2012-008536
Application 11/652,977
1

Technology Center 2600
____________

Before LEE E. BARRETT, CARL W. WHITEHEAD JR., and
JOHNNY A. KUMAR, Administrative Patent Judges.

BARRETT, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1–24. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

THE INVENTION
The invention relates to a scanning line driver circuit for an active
matrix display device. In a gray-scale method for driving light-emitting
elements of pixels, a scanning line selection period is divided between a
writing period, in which a video signal is input to the light-emitting element
to cause light emission, and an erasing period, in which an erasing signal
forcibly turns off the light-emitting element. Spec. ¶¶ 6, 12. In the

1
Title: “Display Device And Electronic Device Having The Same.”
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background art of Fig. 17, a writing scan line driver 301 and an erasing scan
line driver circuit 302 select a scanning line G1 to Gm, and a switching
circuit 303 is provided between both of the scanning line driver circuits and
the scanning lines. Id. ¶ 14. The switching circuit 303 is synchronized with
the first and second half of the scanning time selection period. Id. ¶ 15. In
this embodiment it is necessary to provide a scanning line driver circuit and
switching circuit on both sides of the display area. Id. ¶ 16.
The scanning line driver circuit of the invention uses 4k-stage (k is a
natural number) flip-flop circuits corresponding to each of the m scanning
lines. The output of the fourth stage flip-flop circuit for the i-th scanning
line is connected to the input of the first stage flip-flop circuit for the
(i + 1)-th scanning line as shown in Fig. 1B. As shown in Fig. 2, a scanning
line selection period is divided into half, the first half of the period AP1 is
used for writing video signals into light-emitting elements, and the second
half of the AP2 is used for writing erasing signals for forcibly stopping
current supply to a light-emitting element. Spec. ¶¶ 52–55. Each flip-flop
causes a delay of a half clock cycle. Id. ¶ 52. Therefore, a writing start
pulse (SP) is caused to occur during the AP1 periods and an erasing SP is
caused to occur during the AP2 periods. The advantages are that there is no
need to provide a switching circuit and the scanning line driver can be
arranged on only one side of the display. Id. ¶ 55.
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Claim 1 is reproduced below.
1. A display device comprising:
a scanning line driver circuit; and
m scanning lines (m is a natural number of greater than
or equal to 2) electrically connected to the scanning line driver
circuit,
wherein 4k-stage (k is a natural number) flip-flop circuits
corresponding to each of the m scanning lines are provided in a
shift register included in the scanning line driver circuit,
wherein an output of a fourth stage flip-flop circuit of
4k-stage flip-flop circuits corresponding to an i-th scanning line
(1 ≤ i ≤ m-l) is electrically connected to an input of a first stage
flip-flop circuit of 4k-stage flip-flop circuits corresponding to
an (i + l)-th scanning line, and
wherein a level shifter is configured to amplify directly
an output of the first stage flip-flop circuit of the 4k-stage flip-
flop circuits.

THE PRIOR ART
Anzai et al. (Anzai ’989) US 2003/0209989 A1 Nov. 13, 2003
Anzai et al. (Anzai ’880) US 2005/0205880 A1 Sept. 22, 2005

THE REJECTION
Claims 1–24 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Anzai ’989 in view of Anzai ’880.

ANALYSIS
Initially, it is not clear why claim 1 recites “4k-stage (k is a natural
number) flip-flop circuits corresponding to each of the m scanning lines,”
instead of 4-stage flip-flop circuits. The term “4k-stage (k is a natural
number)” means that there can be 4, 8, 12, etc. stages for k = 1, 2, 3, etc.,
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Application 11/652,977

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respectively. However, because claim 1 recites “an output of a fourth stage
flip-flop circuit of 4k-stage flip-flop circuits corresponding to an i-th
scanning line (1 ≤ i ≤ m-l) is electrically connected to an input of a first
stage flip-flop circuit of 4k-stage flip-flop circuits corresponding to an
(i + l)-th scanning line,” only the first four stages are ever used, so the use of
“k” appears superfluous. Nevertheless, the possible inclusion of additional
unused flip-flops does not make the claims indefinite.
The claims are argued to stand or fall together with independent
claim 1. We agree that claim 1 is representative.
The differences between the gate signal drive circuit in Anzai ’989,
Figure 6, and the scanning line driver circuit of claim 1 are: (1) Anzai ’989
has only a single D-type (delay) flip-flop circuit corresponding to each
scanning line whereas claim 1 recites a “4k-stage (k is a natural number)
flip-flop circuits corresponding to each of the m scanning lines”; and (2) the
output of the flip-flop circuit for an i-th scanning line in Anzai ’989 is
connected to the input of the flip-flop circuit for the (i + 1)-th scanning line
whereas claim 1 recites that “an output of a fourth stage flip-flop circuit of
4k-stage flip-flop circuits corresponding to an i-th scanning line (1 ≤ i ≤ m-l)
is electrically connected to an input of a first stage flip-flop circuit of
4k-stage flip-flop circuits corresponding to an (i + l)-th scanning line.”
The Examiner finds that Anzai ’880 (Fig. 31 and para. 207) teaches
the concept of using flip-flops connected in series to generate a desired delay
for proper timing. Final Act. 5; Ans. 5–6. The Examiner concludes that it
would have been obvious to modify the shift register in Anzai ’989, Fig. 6,
by incorporating additional flip-flops for delay as taught by Anzai ’880 “to
allow the display driver to generate more accurate pixel signal input.”
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Final Act. 5–6; Ans. 6. The Examiner finds that because Appellant has not
disclosed any advantage for using a “4k-stage (k is a natural number) flip-
flop circuits,” concludes that it would have been an obvious matter of design
choice to use 4k-stage flip-flop circuits instead of n-stage flip-flop circuits.
Final Act 6; Ans. 6. The Examiner provides a “Drawing 1” showing how
Anzai ’989 is proposed to be modified by Anzai ’880. Final Act. 7; Ans. 7.
Appellant argues that the Examiner’s Drawing 1 is based on improper
hindsight reconstruction utilizing the claims as a blueprint. App. Br. 16.
Appellant argues that even if one were to modify the shift register of
Anzai ’989 with additional flip-flops, the alleged modified shift register fails
to teach where to provide or how to connect the flip-flops to arrive at the
circuit structure of the claims. Id. at 17. Appellant argues that there is
nothing in Fig. 31 of Anzai ’880 that supports the Examiner’s modification
and it does not teach connecting an output of a fourth stage flip-flop of an
i-the scanning line with an input of a first stage flip-flop of an (i + 1)-th
scanning line. Id. at 17–18. Appellant further argues that to delay pulses
which are outputted from a shift register, a person of ordinary skill in the art
would put flip-flops at the output of the flip-flop between flip-flop 601 and
level shifter 603 in Fig. 6 of Anzai ’989. Id. at 18. “In contrast, the claimed
connection configuration of the present configuration is able to change the
interval between pulses rather than delay pulses themselves which are output
from a shift register.” Id. at 19. The Reply Brief points to the advantages of
the claimed scanning line driver at paras. 75–77 of the publication of the
present application, US 2007/0164939, corresponding to paras. 55–57 of the
application as filed. Reply Br. 4–5.
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Claim 1 is extremely broad because it recites only a sub-combination
of a scanning line driver circuit. For example, it describes the arrangement
and number of flip-flops, but does not recite the type of flip-flop (e.g., a
D-type), and does not recite the use of the clock GCK, the inversion of the
clock GCKB, or the start pulse GSP signals as inputs to the flip-flops or
their connection to the flip-flops (e.g., that clock GCK is input to
odd-number stages and inversion of the clock GCKB is input to
even-numbered stages, Spec. ¶ 44). Claim 1 does not recite the circuit in the
overall display circuit (e.g., that there is only one scanning line driver
circuit). Furthermore, claim 1 is open-ended and does not preclude
additional elements (e.g., a selection circuit). Claim 1 does not recite any
functional language to qualify or explain what function the flip-flops
perform. Nevertheless, there must still be motivation for modifying the
references to arrive at what is claimed.
Anzai ’989 describes separate gate signal drive circuits 403, 404 for
writing and blanking, which are controlled by FPC 407. Anzai ’989,
Figs. 4A and 4B; ¶ 82. A gate signal drive circuit having a single stage
D-type flip-flop (DFF) for each scan line is shown in Fig. 6. As explained in
Anzai ’880, each stage of DFF causes a signal to be delayed by a half cycle
of the clock signal. Anzai ’880 ¶ 204. Thus, the pulse is delayed by a half
cycle on each sequential scan line. The gate signal drive circuits 403, 404 in
Anzai ’989 drive separate gate signal lines for writing 112 and blanking 113
in the pixel circuit shown in Fig. 1D. The scanning line driver structure is
different from claim 1 because it uses a single flip-flop for each scanning
line. Two scanning line driver circuits and two selection circuits are
required to divide the gate selection period into writing and erasing periods.
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Anzai ’880 describes dividing the gate selection period into two
sub-gate selection periods T1 and T2 using two gate driver circuits 41 and
42 on opposite sides of the array, each of which has a selection circuit 55 or
57 . Anzai ’880, Figs. 4 and 11B; ¶¶ 86–90 and 120–129. The gate drivers
correspond to a shift register having a plurality of flip-flop circuits. Id. ¶ 90.
As seen from Fig. 11B, the pulses i, j, k, and p, sequentially output to the
selection circuits on sequential lines are one-half clock period apart,
requiring a single stage flip-flop for each scan line because Anzai ’880
describes that each stage of DFF causes a signal to be delayed by a half
cycle of the clock signal. Id. ¶ 204. The selection circuit 55 is controlled by
the WE (Write/Erase) signal and the selection circuit 57 is controlled by the
inverse of the WE signal. Id. ¶ 88. The scanning line driver structure is
different from claim 1 because it uses a one stage flip-flop for each scanning
line. Two scanning line driver circuits and two selection circuits are
required to divide the gate selection period into writing and erasing periods.
The Examiner provides two reasons for the modification. (To be
clear, the modification requires adding three flip-flop stages to each of the
single flip-flop stages in Anzai ’989, Fig. 6, so that a pulse is delayed two
full clock cycles between scan lines instead of one-half clock cycle.) First,
the Examiner states that Appellant has not disclosed an advantage for
utilizing 4k-stage flip-flop circuits, so the number of flip-flops is a matter of
design choice and it would have been obvious to add number of flip-flops.
Final Act. 5–6; Ans. 6. "Design choice" may be appropriate where applicant
fails to set forth any reasons why the differences between the claimed
invention and the prior art is significant or would result in a different
function or give an unexpected result. See In re Chu, 66 F.3d 292, 298–99
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(Fed. Cir. 1995). Here, however, the Specification describes that a 4-stage
flip-flop circuit causes a writing SP or erasing SP to be delayed by two clock
cycles from the i-th to (i + 1)-th scan lines; this divides the scanning period
into two periods AP1 and AP2 so that all writing SPs fall in an AP1 period
and all erasing SPs fall in an AP2 period. Spec. ¶¶ 49–55. This eliminates
the need to provide a switching circuit and the scanning line driver can be
arranged on only one side of the display. Spec. ¶ 55. Thus, contrary to the
Examiner’s statement that no advantage has been disclosed for “4k-stage”
flip-flop circuits and that the number of stages is a matter of design choice
(Final Act. 5–6; Ans. 6), the 4k-stage flip-flops serve a specific purpose.
The Reply Brief points to the disclosed advantages of the claimed scanning
line driver. Reply Br. 4–5. Therefore, the addition of more flip-flop stages
cannot be dismissed as merely a matter of design choice.
Second, the Examiner finds that Anzai ’880 teaches using delay
flip-flops (DFFs) connected in series to generate a delay for proper timing
and concludes that it would have been obvious to modify Anzai ’989 in view
of Anzai ’880 “to allow the display driver [in Anzai ’989] to generate more
accurate pixel signal input.” Final Act. 5–6; Ans. 6, 22–23. Anzai ’880
describes a WE signal directly inputted to the gate driver and inputted to a
delay circuit before the source driver so that the timing at which the video
signal or the erasing signal changes can be delayed until after the selected
gate is canceled. Anzai ’880 ¶ 203; Fig. 30. The delay circuit may consist
of delay flip-flops (DFFs), as shown in Fig. 31, connected in series, as
shown in Fig. 32. However, the described purpose of the DFFs in
Anzai ’880 is to delay when the video signal or the erasing signal on source
lines Sx (vertical lines S1 to Sm in Fig. 4) change until after the selected
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gate line (horizontal line) is canceled. There is no suggestion or reason in
Anzai ’880 that it might be necessary to provide additional delay between
scan lines for more accurate signal input (or any other reason), much less to
add three flip-flop stages to change the interval between pulses for the
disclosed purpose and advantage. Thus, “that a person having ordinary skill
in the art at the time of the invention would have been able to modify and
combine Anzai 880’ and Anzai 989’” (Ans. 19) does not answer the question
of why the references would have been combined in the manner claimed.
As discussed, the purpose of the three added flip-flop stages is to
divide the gate selection period into two periods AP1 and AP2, so that all
writing SPs fall in an AP1 period and all erasing SPs fall in an AP2 period.
This not suggested in either Anzai ’989 or Anzai ’880. The fact that both
Anzai ’989 and Anzai ’880 utilize only a single stage flip-flop circuits in
their scanning line circuits to delay a pulse by one-half clock cycle weighs
against the obviousness of the modification. Moreover, that the claimed
scanning line driver circuit eliminates the need for a scanning line driver on
the other side of the display and eliminates the need for selection circuits
also weighs against the obviousness of the modification.
For the foregoing reasons, the rejection of claims 1–24 is reversed.

CONCLUSION
The rejection of claims 1–24 is reversed.

REVERSED
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