Ex Parte Mittal et al

Patent Trial and Appeal Board

Oct 24, 2018

14838215 (P.T.A.B. Oct. 24, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/838,215 08/27/2015
123187 7590
Williams Morgan, P.C.
710 N. Post Oak Road
Suite 350
Houston, TX 77024
10/25/2018
FIRST NAMED INVENTOR
Anurag Mittal
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
HMLT025/4014.258700 9717
EXAMINER
TRA, ANH QUAN
ART UNIT PAPER NUMBER
2842
MAIL DATE DELIVERY MODE
10/25/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANURAG MITTAL and MAHBUB RASHED
Appeal2018-001624
Application 14/838,215
Technology Center 2800
Before ROMULO H. DELMENDO, MARK NAGUMO, and LILAN REN,
Administrative Patent Judges.
REN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134 from a rejection2 of claims
1-20. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
1 The Applicant, which is also the real party in interest, is identified as
GLOBALFOUNDRIES, Inc. Application Data Sheet filed August 27, 2015;
Appeal Brief of August 25, 2017 ("App. Br."), 2.
2 Final Office Action of March 27, 2017 ("Final Act."). In this opinion, we
also refer to the Examiner's Answer of October 5, 2017 ("Ans.") and the
Reply Brief of December 1, 2017 ("Reply Br.").
Appeal2018-001624
Application 14/83 8,215
CLAIMED SUBJECT MATTER
The claims seek to "provid[ e] a design for manufacturing a
semiconductor device." Spec. ,r 25. 3 In one embodiment, an "operation
modeling of a semiconductor device circuit design is performed." Id.
Claims 1, 10, and 16, reproduced below, are illustrative of the claimed
subject matter:
1. A method, comprising:
performing an operation modeling of a semiconductor
device circuit design;
identifying at least one transistor for providing at least
one of a first voltage for forward biasing said transistor or a
second voltage for reverse biasing said transistor; and
providing, selectively, a delay for adjusting a timing
associated with said transistor based upon identifying said at
least one transistor.
10. A semiconductor device, comprising:
a first logic circuit;
a second logic circuit;
first interface circuit for operatively coupling said first
logic circuit with said second logic circuit, said first interface
circuit comprising at least one FD SOI transistor; and
a first tunable delay circuit operatively coupled to said
interface circuit, said tunable delay circuit configured for
adjusting an operation timing of said at least one FD SOI
transistor.
16. A system, comprising:
a semiconductor device processing system to process a
semiconductor wafer for manufacturing a semiconductor device
based upon a device design, said semiconductor device
processing system comprising:
a design unit configured to:
3 Specification of Application No. 14/838,215 filed August 27, 2015
("Spec.").
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Application 14/83 8,215
perform an operation modeling of said device design;
identify at least one circuit portion of said semiconductor
device for providing at least one of a first voltage for forward
biasing said transistor or a second voltage for reverse biasing
said transistor; and
provide, selectively, a tunable delay for adjusting a
timing associated with said transistor based upon identifying
said at least one transistor for providing said at least one of a
first voltage for forward biasing said transistor or a second
voltage for reverse biasing said transistor for generating a final
version of said device design;
and
a processing controller operatively coupled to said
semiconductor device processing system, said processing
controller configured to control an operation of said
semiconductor device processing system for manufacturing said
semiconductor device based upon said final version of said
device design.
Claims Appendix.
REFERENCES
The prior art references relied upon by the Examiner in rejecting the
claims on appeal are:
Miyazaki
Komatsu
Searles
US 6,466,077 B 1
US 2008/0143423 Al
US 2012/0066445 Al
REJECTIONS
Oct. 15, 2002
June 19, 2008
Mar. 15,2012
Claims 1, 2, 4--9, 16, and 18-20 are rejected under 35 U.S.C.
§ 102(a)(l) as being anticipated by Miyazaki. Final Act. 2.
Claims 3, 10-13, and 17 are rejected under 35 U.S.C. § 103 as being
unpatentable over Miyazaki and in view of applicant admitted prior art
(AAPA) or Komatsu. Final Act. 4.
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Claims 14 and 15 are rejected under 35 U.S.C. § 103 as being
unpatentable over Miyazaki and in view of applicant admitted prior art
(AAPA) or Komatsu, and in further view of Searles. Final Act. 5.
OPINION
Anticipation of Claim 14
Appellant argues the Examiner reversibly erred because Miyazaki
does not disclose a method step "performing an operation modeling of a
semiconductor device circuit design" as recited in claim 1. App. Br. 6. 5 To
distinguish Miyazaki, Appellant argues that "the operation modeling and
other elements of claim 1 are performed on a 'semiconductor device circuit
design,' and not on a 'semiconductor device' per se." Id. (emphasis in
original). Appellant argues that the operation of the "existing circuit" in
Miyazaki does not disclose that of "a semiconductor device circuit design."
Id. at 8.
Appellant, however, provides no reason to exclude from the recited
"circuit design" a design that is reasonably inferred from a circuit that is
used in actual operation. Appellant, in their Reply Brief, argues that "the
broadest reasonable interpretation of the claim term 'circuit design' is a
design for manufacturing a circuit in a semiconductor device." Reply Br. 2.
Even based on Appellant's own interpretation, the record before us does not
4 Appellants do not present argument separate for the anticipation rejection
of claims 2 and 4--9. App. Br. 9. These dependent claims, namely, claims 2
and 4--9 stand or fall with claim 1 for the anticipation rejection. Id.; see also
37 C.F.R. § 4I.37(c)(l)(iv) (2013).
5 Neither the Appeal Brief nor the Reply Brief is paginated and we therefore
provide our own.
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Application 14/83 8,215
show why the design shown in the operational prior art circuit should be
excluded from the "circuit design" recited in claim 1. As the Examiner
finds, "the 'existing' speed monitor circuit or an actual speed monitor circuit
is built based on the design shown in [Miyazaki] figure 1. Thus, the
'existing' speed monitoring circuit can be considered as a 'model' of the
speed monitor circuit desired in figure 1." Ans. 4. Appellant does not
address this finding by the Examiner (see Reply Br. 2-3) and no reversible
error has been identified.
In arguing for the patentability of claim 1, Appellant also faults the
Examiner for "admitting 'a "circuit design" is just an idea."' Reply Br. 2
( citing Ans. 2 for the Examiner's statement in response to the Appeal Brief).
In so far as Appellant appears to assert that the claim limitation "circuit
design" should be construed as an idea rather than an "existing" physical
device (see id; see also App. Br. 8), an idea is not a patent-eligible subject
matter under section 101 and unpatentability on that additional basis should
be fully explored in the event of further prosecution. 35 U.S.C. § 101.
Appellant's argument that Miyazaki "fail[s] to disclose that the speed
monitor tests for timing errors, determines a design change for reducing
timing errors, and/or determines a design change for improving a
performance of said semiconductor device circuit design" is not persuasive
of harmful error in the rejection of commensurate in scope with claim 1
because it is not directed to limitations recited in the claim. App. Br. 8.
Appellant's unsupported argument that the prior art circuit "would fail to
change the function of the speed monitor circuit" (App. Br. 9; Reply Br. 3) is
similarly directed to features not recited in claim 1 and cannot impart
patentability. In re Self, 671 F.2d 1344, 1348, 213 USPQ 1, 5 (CCPA 1982)
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Application 14/83 8,215
("Many of appellant's arguments fail from the outset because ... they are
not based on limitations appearing in the claims.").
Appellant's conclusory statement that Miyazaki also fails to disclose
the "identifying" and "providing" steps of claim 1 does not address the
Examiner's findings with regard to these steps. Compare App. Br. 9, with
Final Act. 2 ( citing various portions of Miyazaki in support of the rejection,
for example, Figure 4 showing certain delay elements for the "identifying"
step and "delay signal 11" for the step of "providing ... a delay ... ");
compare Ans. 3--4 (citing additional portions of Miyazaki including 8:53-
55, 13: 12-15), with Reply Br. 2-3. No reversible error has therefore been
identified in the Examiner's findings here.
Anticipation of Claim 166
In addition to the arguments raised for claim 1, which we addressed
supra, Appellant argues that Miyazaki does not disclose "a design unit
configured to perform an operation modeling of a semiconductor device
circuit design" as recited in claim 16. App. Br. 10. Appellant urges that the
"closest Miyazaki comes to even discussing manufacturing is in stating that
the device of its invention may be manufactured in higher yield compared to
prior art devices." Id. Appellant argues, without evidentiary support, that a
skilled artisan "would interpret" the prior art "as teaching providing the
design disclosed by Miyazaki to existing manufacturing systems" without
6 Appellants do not present separate argument for the anticipation rejection
of corresponding dependent claims 18-20, App. Br. 11, which stand or fall
with claim 16 for the anticipation rejection. See also 37 C.F.R.
§ 4I.37(c)(l)(iv) (2013).
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explaining why any such existing manufacturing systems are excluded from
claim 16. Id.
The Specification, referring to the Drawings (Figures 10 and 11 ),
provides that "integrated circuit design unit 1140" may, for example
"receive data relating to the design specifications for the integrated circuits
to be designed" and "once a designer or a user of the integrated circuit
design unit 1140 generates a design using a graphical user interface to
communicate with the integrated circuit design unit 1140, the unit 1140 may
perform automated modification of the design." Spec. ,r,r 73, 7 4 ( cited in
App. Br. 4 as written description support for claim 16).
While it is unclear what the structural components of the recited
"design unit" may be, 7 Appellant does not structurally distinguish the prior
art device. Appellant's sole argument is that a skilled artisan "would
interpret" Miyazaki "as teaching providing the design disclosed by Miyazaki
to existing manufacturing systems" instead of "a design unit configured to
7 In cases where review of the rejection under 35 U.S.C. § 103(a) would
require considerable speculation as to the scope of the claims, such
speculation would not be appropriate. In re Steele, 305 F.2d 859, 862
(CCPA 1962) ("[W]e do not think a rejection under 35 U.S.C. § 103 should
be based on such speculations and assumptions."). See also In re
Donaldson, 16 F.3d 1189, 1995 (Fed. Cir. 1994) (en bane) ("[I]f one
employs means-plus-function language in a claim, one must set forth in the
specification an adequate disclosure showing what is meant by that
language."); cf Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1348
(Fed. Cir. 2015) ( en bane) ("[T]he essential inquiry is not merely the
presence or absence of the word 'means' but whether the words of the claim
are understood by persons of ordinary skill in the art to have a sufficiently
definite meaning as the name for structure."). In this case, however, the
review of the anticipation rejection does not require considerable speculation
as to the scope of the claims because Appellant's argument is essentially an
unelaborated disagreement with the rejection.
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Application 14/83 8,215
perform an operation modeling of a semiconductor device circuit design."
App. Br. 10. Without structural distinction over the prior art, however, we
are not persuaded that the Examiner reversibly erred here. See Hewlett-
Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1468 (Fed. Cir. 1990)
("[A]pparatus claims cover what a device is, not what a device does.").
We additionally note that the Examiner finds that the prior art device
is capable of achieving such as purpose - a finding to which Appellant does
not respond substantively and is therefore unrefuted. Compare Ans. 4, with
Reply Br. 2-3. Based on these reasons, no reversible error has been
identified here.
Obviousness of Claims 3 & 17
Claim 3 depends on claim 1 and further recites "wherein identifying at
least one transistor comprises identifying at least one of an FD SOI L VT
transistor, an FD SOI SLVT transistor, an FD SOI RVT transistor, an FD
SOI HVT transistor, or a combination thereof."
For the obviousness rejection based on Miyazaki and AAP A or
Komatsu, Appellant argues that one particular portion of Miyazaki "clearly
states that Miyazaki's main circuit may have an operating speed that is
undesirably high" which would fail to motivate the skilled artisan "to replace
Miyazaki's transistor(s) with an FD SOI transistor and have a reasonable
expectation of success." App. Br. 11-12 (citing Miyazaki 8:20-51).
As the Examiner points out, the teaching in Miyazaki is not limited to
the example of a high speed main circuit. Ans. 5. The Examiner cites other
portions of Miyazaki in support of the rejection - for example, Miyazaki
"teaches that the invented circuit is satisfied with the high operating speed
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Application 14/83 8,215
and the low electric power consumption" which would lead the skilled
artisan to use an FD SOI transistor for "improving the circuit speed." Id.
(citing Miyazaki 7:57---61).
The test of obviousness is "whether the teachings of the prior art,
taken as a whole, would have made obvious the claimed invention." In re
Gorman, 933 F.2d 982, 986 (Fed. Cir. 1991). Appellant does not address
the Examiner's finding based on Miyazaki's teachings as a whole.
Appellant does not dispute that FD SOI transistors are known in the art and
do not argue that the combined prior art teachings "do more than yield a
predictable result." See KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,416
(2007) ("[W]hen a patent claims a structure already known in the prior art
that is altered by the mere substitution of one element for another known in
the field, the combination must do more than yield a predictable result.")
(citing United States v. Adams, 383 U.S. 39, 50-51 (1966)). For these
reasons, we are not persuaded that the Examiner reversibly erred in rejecting
claim 3.
Claim 1 7 depends from claim 16 and further recites "wherein said
design unit is further configured to identify at least one of an FD SOI LVT
transistor, an FD SOI SLVT transistor, an FD SOI RVT transistor, or an FD
SOI HVT transistor." Appellant's arguments for claim 17 are identical to
those for claims 16 and 3 (compare App. Br. 10, 11, with id. at 14) which we
addressed supra as not persuasive to identify reversible error.
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Obviousness of Claim 108
In addition to the arguments we addressed supra (App. Br. 13
( arguing for the patentability of claim 10 "[ f]or reasons discussed above
regarding claim 3")), Appellant argues that the Examiner reversibly erred
because Miyazaki "teaches that its speed monitor circuit outputs the
operating speed of the main circuit" but does not teach or suggest that "its
speed monitor circuit is operatively coupled to the main circuit and is
configured for adjusting an operation timing of at least one transistor in the
main circuit." App. Br. 12-13. Appellant also argues that Miyazaki
"adjusts the operating speed of the main circuit by adjusting the substrate
bias of the circuit as a whole" but does not teach or suggest "adjusting the
operation timing of any specific transistor(s) in the main circuit." Id. at 13.
Both arguments are conclusory and unsupported by evidence.
"Attorneys' argument is no substitute for evidence." Johnston v. IVAC
Corp., 885 F.2d 1574, 1581 (Fed. Cir. 1989). Appellant does not address the
Examiner's findings in support of the rejection. Compare Ans. 5 (citing
Miyazaki 8:20-30 as well as various components and nodes in Miyazaki
Figs. 1, 2, and 4), with Reply Br. 4. Other than stating its disagreement over
the rejection, Appellant does not explain why the Examiner reversibly erred
in evaluating Miyazaki's teachings. Based on the record before us, no
reversible error has been identified for the rejection of claim 10. See
37 C.F.R. § 4I.37(c)(l) (iv) (2013); see also In re Jung, 637 F.3d 1356,
8 Appellant does not present argument separate for the obviousness rejection
of claims 11-13 App. Br. 12-13, so these claims stand or fall with claim 10
for the obviousness rejection. Id.; see also 37 C.F.R. § 4I.37(c)(l)(iv)
(2013).
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1365 (Fed. Cir. 2011) ("[I]t has long been the Board's practice to require an
applicant to identify the alleged error in the examiner's rejections .... ").
Obviousness of Claim 14
In arguing for the patentability of claim 14 which depends from claim
10, Appellant does not dispute the prior art teachings but argues that a
skilled artisan "would lack any motivation" to combing the prior art
teachings. App. Br. 16. Appellant reasons that the skilled artisan would not
have a reasonable expectation of success because "delaying strobe signals to
ensure correct latching of data signals" taught in Searles "is different from
adjusting the operating speed of a circuit" taught in Miyazaki. Id.
Appellant, however, does not explain why combining these known structures
would "do more than yield a predictable result." See KSR, 550 U.S. at 416
("[W]hen a patent claims a structure already known in the prior art that is
altered by the mere substitution of one element for another known in the
field, the combination must do more than yield a predictable result."); In re
0 'Farrell, 853 F.2d 894, 903 (Fed. Cir. 1988) (["Obviousness does not
require absolute predictability of success."). Appellant does not address the
Examiner's rationale that a skilled artisan would "use one of the modified
[Miyazaki's] interface circuits to couple between a processor and a memory
circuit for the purpose of providing precise communication between the
memory device and the processor." Compare App. Br. 16, with Final Act. 5
& Ans. 7. Appellant does not dispute the Examiner's finding supporting that
"Miyazaki and Searles show similar circuits." Compare Ans. 6 (citing
various portions of Miyazaki and Searles), with Reply Br. 4. Appellant has
therefore failed to identify reversible error in the rejection of claim 14
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Obviousness of Claim 15
In arguing for the patentability of claim 15, Appellant argues that the
combined prior art does not teach or suggest "a voltage source for providing
at least one of a forward bias voltage and a reverse bias voltage" because of
"the failure of Searles to use the word 'reverse"' and "Searles' only use of
the word 'forward."' App. Br. 17. The test for obviousness does not require
the prior art reference to use the exact phrase as the claim but "whether the
teachings of the prior art, taken as a whole, would have made obvious the
claimed invention." Gorman, 933 F.2d at 986. Appellant's argument is also
not persuasive because the claim only requires "at least one of a forward bias
voltage and a reverse bias voltage," but not both. We further note that
Appellant does not respond to the Examiner's finding that when "Searles'
drivers are replaced with Miyazaki's driver," the resulting device "shows the
operation to provide forward and reverse bias voltages to its drivers."
Compare Ans. 7-8 (citing Miyazaki 8:53-55), with Reply Br. 4. We are
therefore not persuaded that reversible error has been identified in the
current record for claim 15.
DECISION
The Examiner's decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a) (2013). See 37
C.F.R. § 1.136(a)(l)(iv) (2013).
AFFIRMED
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