Ex Parte Minnick et al

Board of Patent Appeals and Interferences

Aug 30, 2012

10007082 (B.P.A.I. Aug. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/007,082 12/06/2001 Linden Minnick P12249 3183
76973 7590 08/30/2012
The Law Offices of Christopher K. Gagne
c/o CPA Global
B.O. Box 52050
Minneapolis, MN 55402
EXAMINER
MADAMBA, GLENFORD J
ART UNIT PAPER NUMBER
2451
MAIL DATE DELIVERY MODE
08/30/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte LINDEN MINNICK and PATRICK L. CONNOR
____________________

Appeal 2010-006764
Application 10/007,082
Technology Center 2400
____________________

Before JOSEPH L. DIXON, THU A. DANG,
and JAMES R. HUGHES, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-311. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
Appellants’ invention is directed to an Input/Output (I/O) device and
method for processing latency (time) sensitive electronic data; wherein, the
I/O device includes a parsing module which passes information about the
characteristics of the data to an interrupt management module that generates
an interrupt scheme based on the characteristics of the data (Abstract; Spec.
9:26-10:24).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary:
1. An apparatus comprising:

an input/output (I/O) device operative to:

receive a fragment of electronic data from a node
on a network;

determine characteristics of the fragment of
electronic data;

moderate one or more interrupts to a processor if
the characteristics of the fragment of electronic data

1 After reviewing the record, although Appellants note that claims 21-35 are
on appeal (App. Br. 4), we consider this notation a typographical error since
the status of the claims recites the claims 1-31 are rejected and Appellants
present arguments for claims 1-31.
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indicate that the fragment of electronic data is
latency-sensitive data.

C. REJECTION
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Johnson US 5,905,874 May 18, 1999
Drottar US 6,333,929 B1 Dec. 25, 2001
Gentry US 6,434,651 Bl Aug. 13, 2002
(filed Mar. 01, 1999)
Duda US 7,065,762 Bl Jun. 20, 2006
(filed Mar. 22, 1999)

Claims 1, 3, 5, 11, 20, 232, and 29 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Johnson in view of Duda.
Claims 2, 4, 12, 13, 21, 22, 30, and 31 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Johnson in view of Duda and Drottar.
Claims 6-10, 15-19, and 24-28 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Johnson in view of Duda and Gentry.

II. ISSUES
The dispositive issue before us is whether the Examiner has erred in
concluding that the combination of Johnson and Duda teaches or would have
suggested “moderate one or more interrupts to a processor if the
characteristics of the fragment of electronic data indicate that the fragment
of electronic data is latency sensitive data” (claim 1, emphasis added). In
particular, the issue turns upon whether the combination of Johnson and

2 Although there is no corresponding rejection for claim 23 (depending from
claim 20), rejected claim 5 (depending from claim 1) includes similar claim
language. Thus, we consider claim 23 rejected with its parent claim 20.
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Duda discloses or would have suggested an I/O device that interrupts a
processor if the received data is latency sensitive.

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Johnson
1. Johnson discloses a network device (computer) including its
network interface card (NIC) having a buffer for storage of data transferred
between the network device and the network (col. 1, ll. 58-62 and col. 2, ll.
27-30). For Direct Memory Access (DMA) capable systems, the NIC
controls the data transfer from the NIC to the main memory of the computer;
wherein, at the completion of the transferred data, the NIC informs the host
processor using an interrupt signal (col. 2, ll. 42-48 and ll. 55-59). In the
alternative, for memory-mapped configurations, the NIC informs the
processor by interrupt that data has been written into its buffer and, in
response, the host processor controls the transfer of data from the buffer to
the computer memory (col. 2, ll. 47-50).
Duda
2. Duda discloses a data switch 200 that examines the contents of
received data packet(s) to determine whether the data is latency-sensitive
with the purpose of meeting its particular service requirements; wherein, the
data is placed in a queue for a particular destination output port (col. 5, ll. 9-
20).
3. The data switch includes a borrowed-virtual-time (BVT)
scheduler which allocates the time that the output port is available to a queue
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(col. 4, ll. 63-66 and col. 5, ll. 54-56). The BVT scheduler includes a
preemptive scheduling process that is initiated with a system timer interrupt
signal to the processor (col. 5, ll. 57-64).

IV. ANALYSIS
Claims 1, 3, 5, 11, 20, 23, and 29
Appellants contend that “Duda does not teach moderating interrupts
based on the characterization that received data fragments are latency
sensitive,” “[r]ather, Duda discloses a network switch that examines the
contents of received data packets and determines an appropriate queue based
on that content” (App. Br. 10). Appellants also assert that “the references
give no incentive or motivation to modify either reference to include the
feature” (id.). According to Appellants, “Johnson actually teaches away”
since “[i]t states that memory mapped schemes, which use interrupts to
invoke the host processor to service network interface data transfer tasks, are
less desirable than direct memory access (DMA) methods because they
involve inefficiency and require valuable host processor resources” (App.
Br. 10-11).
However, the Examiner finds that “Johnson expressly discloses the
use and/or employment of interrupts (i.e., ‘notifications’ / ‘interrupts’ to the
processors of data transfers and/or requests for data transfers) for exemplary
prior art embodiments that utilize a memory-mapped system or,
alternatively, DMA systems” (Ans. 22). The Examiner finds that “the
argued limitation of ‘determining whether characteristics of the fragments of
electronic data are latency-sensitive’ by an apparatus that employs or works
in concert with ‘interrupts’ is expressly disclosed by Duda” (Ans. 28);
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wherein, “Duda expressly discloses that Data Switch 200 examines the
contents of the data packet and determines the ‘service requirements’” such
that “latency sensitive data packets can be placed in a different queue than
latency insensitive packets, or multicast packets” (Ans. 29).
The Examiner finds further that “Duda also teaches that [a]
preemptive scheduling algorithm [which is interrupt driven and] can be
performed / implemented by … [the] Data Switch 200” (id.). The Examiner
notes that “the disclosures of Johnson and Duda make it clear that both
Johnson and Duda are, in fact, related endeavors that seek to reduce the
‘latency’ of their respective system in the processing of data received by a
NIC device” (Ans. 31).
We give the claim its broadest reasonable interpretation consistent
with the Specification. See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
1997).
Claim 1 does not place any limitation on what “moderate” means,
includes, or represents. The Specification is silent as to a definition for the
claim term other than noting that the interrupt management module
moderates the interrupt scheme for the I/O device (Spec. 10:15-18). Thus,
we give “moderate one or more interrupts to a processor” its broadest
reasonable interpretation as actuation of one or more interrupts to the
processor, as consistent with the Specification and as specifically recited in
claim 1.
Johnson discloses an NIC that issues an interrupt to the host processor
before a data transfer (in memory-mapped configurations) or after a data
transfer (in DMA capable systems) (FF 1). We find that the issuance of an
interrupt signal to the host computer comprises actuation of an interrupt to
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the processor. That is, in view of our broad but reasonable claim
interpretation, we find that Johnson’s interrupt feature of the NIC comprises
a step to “moderate one or more interrupts to a processor” as required by
claim 1.
In addition, Duda is directed to a data switch that examines the
contents of a received data packet to determine whether the data is latency-
sensitive with the purpose of meeting its particular service requirement (FF
2). The data switch also includes a BVT scheduler including a preemptive
scheduling process that initiates a system timer interrupt signal to the
processor (FF 3). We find that examination of the data by the data switch
comprises determining if the data is latency sensitive data.
We find further that the data switch initiates a system timer interrupt
signal to the processor which comprises actuation of an interrupt to the
processor whether or not the data is latency sensitive. That is, the data
switch initiates a system timer interrupt signal if the data is latency sensitive
as well as if the data is not latency sensitive. Accordingly, we find that
Duda’s data switch having a preemptive scheduling process comprises
moderating interrupts to a processor “if the characteristics of the fragment of
electronic data indicate that the fragment of electronic data is
latency-sensitive data” as required by claim 1.
In view of our claim construction above, we find that the combination
of Johnson and Duda at least suggests providing a step to “moderate one or
more interrupts to a processor if the characteristics of the fragment of
electronic data indicate that the fragment of electronic data is
latency-sensitive data,” as required by claim 1.
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Though Appellants also contend that the combination “teaches away”
since Johnson discloses “that memory mapped schemes, which use
interrupts to invoke the host processor to service network interface data
transfer tasks, are less desirable than direct memory access (DMA) methods”
(App. Br. 10-11), our reviewing court has held that “‘[a] reference may be
said to teach away when a person of ordinary skill, upon [examining] the
reference, would be discouraged from following the path set out in the
reference, or would be led in a direction divergent from the path that was
taken by the applicant.’” Para-Ordnance Mfg., Inc. v. SGS Importers Int’l.,
Inc., 73 F.3d 1085, 1090 (Fed. Cir. 1995) (quoting In re Gurley, 27 F.3d
551, 553 (Fed. Cir. 1994)).
Appellants have identified no express support for a direction
divergent from the claimed invention since both the memory-mapped and
the DMA schemes both include interrupts to the host processor. Here, the
Appellants appear to have viewed the reference from a different perspective
than the Examiner. The issue here is not whether one scheme is less
desirable than the other but rather whether a person of ordinary skill, upon
reading Johnson, would be discouraged from using the method of
determining whether the data is latency sensitive as taught by Duda.
We also agree with the Examiner’s explicit motivation that combining
the references would be obvious since there is a need for “advantageously
scheduling a resource between elements to maintain a fair long-term
allocation of the resource to elements while still satisfying the responsive
needs of latency-sensitive elements and to improve device performance”
(Ans. 6). The Supreme Court has stated that “[t]he combination of familiar
elements according to known methods is likely to be obvious when it does
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no more than yield predictable results.” KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 416 (2007).
Thus, we find no error in the Examiner’s finding that the combination
of Johnson’s network device (computer) including NIC that issues an
interrupt signal to the host processor with the network device (data switch)
that transfers data based upon a determination of whether the data is latency
sensitive, as disclosed in Duda, produces actuating of one or more interrupts
to a processor if the electronic data is latency sensitive which would be
obvious (Ans. 6; FF 1-3).
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a) over Johnson
in view of Duda. Further, independent claims 11 and 20 and claims 3, 5, 23,
and 29 (depending from claims 1 and 20) having similar claim language,
which have not been argued separately, fall with claim 1.
Claims 2, 4, 6-10, 12, 13, 15-19,
21, 22, 24-28 30, and 31

Appellants argue that claims 2, 4, 6-10, 12, 13, 15-19, 21, 22, 24-28
30, and 31 are patentable over the cited prior art for the same reasons
asserted with respect to claim 1 (App. Br. 11-12).
As noted supra, however, we see no deficiencies in the combined
teachings of Johnson and Duda. We therefore also affirm the Examiner’s
rejection of claims 2, 4, 12, 13, 21, 22, 30, and 31 over Johnson in further
view of Duda and Drottar and of claims 6-10, 15-19, and 24-28 over
Johnson in further view of Duda and Gentry.

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V. CONCLUSION AND DECISION
The Examiner’s rejection of claims 1-31 under 35 U.S.C. § 103(a) is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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