Ex Parte Mills et al

Patent Trial and Appeal Board

Feb 23, 2017

13707396 (P.T.A.B. Feb. 23, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/707,396 12/06/2012 Peter C. Mills NVDA/SC-12-0290-US1 3807
102324 7590 02/27/2017
Artegis Law Group, LLP/NVIDIA
7710 Cherry Park Drive Suite T #104
Houston, TX 77095
EXAMINER
AMOROSO, ANTHONY J
ART UNIT PAPER NUMBER
2113
NOTIFICATION DATE DELIVERY MODE
02/27/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
kcruz @ artegislaw.com
ALGdocketing @ artegislaw.com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NVIDIA CORPORATION
Appeal 2016-0020521
Application 13/707,396
Technology Center 2100
Before ERIC B. CHEN, KEVIN C. TROCK, and AMBER L. HAGY,
Administrative Patent Judges.
HAGY, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant seeks review under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—3, 5, 6, 9—13, 16—18, and 21, which are all of the
pending claims.2 We have jurisdiction over these claims under 35 U.S.C.
§ 6(b).
We affirm.
1 The real party in interest is identified as NVIDIA Corporation. (App. Br.
3.) The named inventors are Peter C. Mills and Gautam Bhatia.
2 Claims 4, 7, 8, 14, 15, 19, and 20 have been canceled. (App. Br. 15—17
(Claims App’x).)
Appeal 2016-002052
Application 13/707,396
Introduction
According to Appellant, “[t]he present invention relates generally to
the field of integrated circuit interface debugging and, more specifically, to
an internal logic analyzer with programmable window capture.” (Spec. 1.)
Exemplary Claim
Claim 1, reproduced below with the disputed limitation italicized, is
exemplary of the claimed subject matter:
1. A method for capturing debug data within a processing
unit, the method comprising:
receiving a data signal transmitted to the processing unit;
analyzing the data signal and generating feedback information
related to the data signal; and
capturing the data signal via a write enable during a plurality of
clock cycles specified by a programmable controller included
within the processing unit, wherein the write enable is activated
by the programmable controller at a programmed point in time.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Creigh US 2006/0036919 A1 Feb. 16,2006
Johnson et al. US 7,809,991 B2 Oct. 5,2010
Vermeulen, Bart, “Functional Debug Techniques for Embedded
Systems,” IEEE Design & Test of Computers (May/June 2008), pp.
208-215.
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Application 13/707,396
REJECTIONS
Claims 1—3, 9—11, 16, 17, and 21 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Johnson and Creigh. (Final Act. 2—10,
14—17.)
Claims 5, 6, 12, 13, and 18 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Johnson, Creigh, and Vermeulen. (Final Act. 10—
14.)
ISSUE
Whether the Examiner erred in finding Creigh teaches or suggests
“wherein the write enable is activated by the programmable controller at a
programmed point in time,” as recited in independent claim 1 and
commensurately recited in independent claims 10 and 17.
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments the Examiner has erred. We disagree with Appellant’s
conclusions and we adopt as our own: (1) the findings and reasons set forth
by the Examiner in the action from which this appeal is taken (Final Act. 2—
17) and (2) the reasons set forth by the Examiner in the Examiner’s Answer
in response to Appellant’s Appeal Brief. (Ans. 2—19.) We concur with the
conclusions reached by the Examiner, and we highlight the following for
emphasis.3
3 Only those arguments made by Appellant have been considered in this
decision. Arguments Appellant did not make in the briefs have not been
considered and are deemed to be waived. See 37 C.F.R. § 41.37(c)(l)(iv).
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Application 13/707,396
The Examiner finds Johnson teaches all the limitations of claim 1,
except Johnson “does not explicitly disclose . . . wherein the write enable is
activated by the programmable controller at a programmed point in time.”
(Final Act. 2—3.) The Examiner relies on Creigh and finds:
Creigh teaches a programmable embedded logic analyzer that
can store data into memory (Creigh: | [0014]; | [0024]). The
programmability of the logic analyzer allows the user to set and
define various trigger conditions to start the monitoring and data
capturing process (Creigh: | [0016]). Creigh further teaches the
use of clock selectors, the use of a delay circuit with a clock
signal, and the use of a decimator on the clock signal (Creigh: |
[0034] - [0039]). These elements are used to define the data
capture window by manipulating the clock used for capturing the
data. By setting certain trigger conditions at a particular time
and manipulating the data capture clock to define a data capture
window, the user can activate the data capture at a
“programmedpoint in time. ”
(Final Act. 4 (emphasis added).)
Appellant argues Creigh’s “delay circuit merely alters the manner in
which data is captured from the bus, enabling the logic analyzer to be
adapted to capture different types of data signals.” (App. Br. 11.) Appellant
further argues “Creigh does not disclose that the delay circuit is in any way
related to the write enable function of the logic analyzer.” (Id. )
Accordingly, Appellant argues, Creigh’s “delay circuit cannot and does not
cause the logic analyzer to activate a write enable function at a programmed
point in time.” (Id.; see also Reply 6.)
We disagree. The Examiner finds, and we agree,
Creigh teaches that the user can set and define various trigger
conditions to start the monitoring and data capturing process
(Creigh: | [0016]). These trigger conditions are considered
“soft” triggers since they are programmable. Creigh further
teaches the use of clock selectors, the use of a delay circuit with
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Application 13/707,396
a clock signal, and the use of a decimator on the clock signal
(Creigh: | [0034] - [0039]). These elements are used to define the
capture window by manipulating the clock to define clock cycles
used for capturing the data. As shown in Creigh’s Figure 2B,
the clock delay is applied prior to the capture of data signals and
the occurrence of trigger events (Creigh: Figure 2B, steps 245,
250, and 255). The occurrence of a trigger event results in data
being stored from the data capture register into memory (Creigh:
Figure 2B, step 260). The trigger event therefore functions as a
write enable signal to write data into memory.
Creigh further teaches that the sampling clock signal,
which is subject to the clock delay, is used as an input to the
trigger and monitoring section, which contains a monitor signal
selector, a data capture register, a trigger source selector, and a
trigger control logic circuit (Creigh: | [0027] — [0029]). Since
the trigger selector and control logic uses the sampling clock
signal, which is subject to delay and/or decimation, the
generation of trigger events are therefore also subject to the
sampling clock signal and any associated delays/decimations.
(Ans. 16 (emphases added).) Also supporting the Examiner’s findings is
Creigh’s teaching that “sampling data signals from one of the plurality of
buses using the embedded logic analyzer” also comprises “collecting data
signals from the selected bus on a data capture register in response to the
sampling-clock. . . .” (Creigh, claims 1 and 3 (emphasis added).) As Creigh
further teaches, a “data capture register block 324 is coupled to the memory
340, which writes data into the memory 340 in response to the logic analyzer
state control machine 330.” (Creigh 128 (emphasis added).) Thus, as the
Examiner correctly finds, Creigh discloses a “write enable” as part of the
process of capturing a data signal, and discloses this process of capturing a
data signal is subject to the sampling clock signal, which may be subject to a
delay; therefore, the “write enable” is activated at a “programmed point in
time,” as recited in claim 1. (Ans. 16.)
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Application 13/707,396
Appellant’s argument that “Creigh relies on defining specific trigger
conditions . . . which may or may not occur at some indeterminate point in
time” (Reply Br. 6) is not persuasive because claim 1 does not preclude a
trigger condition as being part of the activation process. The Examiner
finds, and we agree, claim 1 “does not specifically define ‘a programmed
point in time,”’ (Ans. 15.), nor does Appellant point to teachings in the
Specification that would constrain that phrase. The Examiner correctly finds
that Creigh’s “write enable” is activated at a “programmed point in time”
because the “write enable” is subject not only to the trigger condition but
also is subject to the sampling clock signal, which may be subject to a delay.
(Ans. 16 (citing Creigh || 16, 27—29, 34—39, Fig. 2B).) We are not
persuaded of error in the Examiner’s finding that Creigh’s teachings are
within the broadest reasonable interpretation of “programmed point in time.”
For the foregoing reasons, we are not persuaded of error in the
Examiner’s 35 U.S.C. § 103(a) rejection of independent claim 1 and we,
therefore, sustain that rejection. Appellant argues the rejection of
independent claims 10 and 17, and dependent claims 2, 3, 9, 11, 16, and 21,
collectively with claim 1. (App. Br. 13.) We, therefore, sustain the rejection
of those claims for the same reasons as for claim 1. See 37 C.F.R.
§ 41.37(c)(l)(iv).
Appellant does not present separate substantive arguments for the
patentability of dependent claims 5, 6, 12, 13, and 18, which stand rejected
under 35 U.S.C. § 103(a) over Johnson, Creigh and Vermeulen. (Final Act.
10—14.) Appellant argues only that the Examiner’s additional citation
Vermeulen “fails to cure the deficiencies of Johnson and Creigh . . .”
asserted with regard to claims 1, 10, and 17. (App. Br. 13.) Because, as
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Application 13/707,396
stated above, we do not find the combination of Johnson and Creigh to be
deficient with regard to independent claims 1, 10, or 17, we also sustain the
Examiner’s § 103(a) rejection of dependent claims 5, 6, 12, 13, and 18.
DECISION
For the above reasons, the Examiner’s rejections of claims 1—3, 5, 6,
9—13, 16—18, and 21 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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