Ex Parte Merritt

Patent Trial and Appeal Board

Jun 16, 2016

12797350 (P.T.A.B. Jun. 16, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121797,350 06/09/2010
15747 7590 06/20/2016
Dorsey & Whitney LLP-IP Dept.-MTI
Columbia Center
701 5th Avenue, suite 6100
Seattle, WA 98104-7043
FIRST NAMED INVENTOR
Todd A. Merritt
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
500345.04 I
P029616.US.03
4597
EXAMINER
TRAN, DENISE
ART UNIT PAPER NUMBER
2138
NOTIFICATION DATE DELIVERY MODE
06/20/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ip.docket.se@dorsey.com
bingemang@dorsey.foundationip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TODD A. MERRITT
Appeal2014-003836
Reissue Application 12/797,350
U.S. Patent 5,983,314
Technology Center 2100
Before CAROLYN D. THOMAS, JASON V. MORGAN, and
DANIEL GALLIGAN, Administrative Patent Judges.
THOMAS, Administrative Patent Judge.
DECISION ON APPEAL
Appellant seeks our review under 35 U.S.C. § 134(a) of the
Examiner's rejection of claims 68-85. We have jurisdiction over the appeal
under 35 U.S.C. § 6(b).
We AFFIRM.
The present application on appeal is a continuation of Application No.
10/006,785 (Nov. 9, 2001) which seeks to reissue U.S. Patent RE41441
("the '441 patent") which is a reissue of 08/898, 177 (July 22, 1997) U.S.
Patent 5,983,314 ("the '314 patent").
Appeal2014-003836
Application 12/797,350
Appellant's invention relates to "a data output buffer which may be
used in a memory device in which a data masking control signal is
inherently synchronized to data coupled through the buffer." See generally
'314 Patent, col. 1, 11. 6-8.
Claim 76 is illustrative:
76. A data coder, comprising:
a data mask register configured to receive a data
mask input signal and output a data mask out signal a
predetermined period after receipt of the data mask input signal,
the data mask register comprising:
a latency control circuit configured to
receive a latency control signal and configured to adjust the
latency of the data mask out signal responsive to receipt of the
latency control signal; and
a terminal configured to receive a clock
signal, the data mask out signal configured to change state
responsive to at least one of a rising edge of the clock signal or
a falling edge of the clock signal; and
a data output register coupled to the data mask
register and configured to couple predetermined signals to a
first data bus responsive to receipt of the data mask out signal,
the data output register further configured to receive data on a
second data bus.
Appellant appeals the following rejections: 1
RI. Claim 68-85 are rejected under 35 U.S.C. § 251 as being based
upon a defective reissue (Final Act. 2; see also App. Br. 3).
R2. Claims 54--71 are rejected under 35 U.S.C. § 251 as being based
upon a defective reissue declaration (Final Act. 3; see also App. Br. 3).
1 The Examiner withdrew the rejection of claims 68-85 under
35 U.S.C. § 251 as being improperly broadened in a reissue application filed
outside the two-year statutory period (see Ans. 6). The Examiner also
withdrew the objections to the drawings (id. at 7).
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Appeal2014-003836
Application 12/797,350
R3. Claim 76-85 are rejected under 35 U.S.C. § 102(e) as being
anticipated by Dosaka (US 5, 777 ,942) (Final Act. 16; see also App. Br. 3).
THE DEFECTIVE REISSUE AND DEFECTIVE DECLARATION
REJECTION UNDER § 251 (RI & R2)
Appellant did not present any arguments pertaining to the Examiner's
rejection of claims 68-85 under 35 U.S.C. § 251 as being based upon a
defective reissue nor the rejection of claims 54--71under35 U.S.C. § 251 as
being based upon a defective reissue declaration (see App. Br. 7-10; see
also Reply Br. 2-3). Accordingly, we summarily sustain these rejections.
REJECTION UNDER§ 102(e)
Claims 76---85 (R3)
Issue: Did the Examiner err in finding that Dosaka discloses to adjust
the latency of the data mask out signal responsive to receipt of the latency
control signal, as set forth in claim 76?
Appellant contends:
The clock mask circuit 130 receives the clock mask signal and
an internal clock signal. Neither of these signals are analogous
to a latency control signal. Moreover, the clock mask circuit
130 is not described as being configured to adjust the latency of
the clock mask signal responsive to receipt of the latency
control signal. The clock mask circuit 130 always provides a
clock mask signal having a delay of 1 clock cycle period
regardless of the latency.
(App. Br. 9). Appellant further contends that "Dosaka does not describe the
shift register 152 as adjusting a latency based on the internal clock signal
Ki .... The amount of delay provided by the shift register 152 (i.e., one
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Appeal2014-003836
Application 12/797,350
clock period) is fixed, and does not change based on a read latency" (Reply
Br. 3). We are persuaded by Appellant.
The Examiner finds that in Dosaka the "'Mask circuit 130 includes
shift register 152 responsive to the internal clock Ki for providing a delay of
1 clock cycle period ... therefore[,]' the internal clock Ki is a latency
control signal" (Ans. 8). Although we agree with the Examiner that
Dosaka's Ki signal acts as a latency control signal, we find that the
Examiner has merely shown that this Ki signal "provides" (or triggers) a
delay as opposed to "adjusting" a delay, as required by the claims. The
Examiner reasons that "the mask circuit 13 0 changed the latency from a
delay of 0 clock cycle period to 1 clock cycle of the clock mask signal CMs
responsive to receipt of the latency control signal Ki" (id.). In other words,
the Examiner interprets Dosaka as disclosing adjusting a delay from 0 clock
cycle to 1 clock cycle. However, we find that one of ordinary skill in the art
would recognize that going from a delay of 0 clock cycle to 1 clock cycle is
equivalent to going from no delay to a delay of 1 clock cycle, which is
adding a delay as opposed to adjusting a delay. Claim 76 recites outputting
a data mask out signal a predetermined period after receipt of the mask input
signal and adjusting the latency of the data mask out signal (see claim 7 6).
In other words, the claims require starting with a delay and then adjusting
that delay. We agree with Appellant that Dosaka' s amount of delay
provided by the shift register 152 (i.e., one clock period) is fixed and does
not change based on a control signal (see Reply Br. 3).
Thus, we disagree with the Examiner's finding that Dosaka discloses
adjusting a latency, as recited in each of the independent claims. Since we
agree with at least one of the arguments advanced by Appellant, we need not
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Appeal2014-003836
Application 12/797,350
reach the merits of Appellant's other arguments. Accordingly, we will not
sustain the Examiner's anticipation rejection of claims 76-84 over Dosaka.
DECISION
We reverse the Examiner's§ 102(e) rejections of claims 76-85.
We affirm the Examiner's rejection of claims 68-85 under 35 U.S.C.
§ 251 as being based upon a defective reissue and the rejection of claims 54--
71under35 U.S.C. § 251 as being based upon a defective reissue
dee larati on.
Since at least one rejection encompassing all claims on appeal is
affirmed, the decision of the Examiner is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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