Ex Parte MANZI et al

Patent Trial and Appeal Board

Sep 24, 2018

12963337 (P.T.A.B. Sep. 24, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/963,337 12/08/2010
65913 7590 09/26/2018
Intellectual Property and Licensing
NXPB.V.
411 East Plumeria Drive, MS41
SAN JOSE, CA 95134
FIRST NAMED INVENTOR
Giuliano MANZI
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
81407530US01 2658
EXAMINER
SHERWIN,RYANW
ART UNIT PAPER NUMBER
2686
NOTIFICATION DATE DELIVERY MODE
09/26/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GIULIANO MANZI and GERALD WIEDNIG
Appeal2018-003675
Application 12/963,337
Technology Center 2600
Before ERIC S. FRAHM, JOHN A. EV ANS, and JOHN P. PINKERTON,
Administrative Patent Judges.
EV ANS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek our review under 35 U.S.C. § 134(a) from the
Examiner's final rejection of Claims 1---6, 8, 9, and 16-25. App. Br. l; Final
Act 2. Claims 7 and 10-15 are canceled. App. Br. 3; Final Act 2. We have
jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE. 2
1 Appellants state the real party at interest is NXP B.V., App. Br. 3.
2 Rather than reiterate the arguments of the Appellants and the Examiner, we
refer to the Appeal Brief (filed October 31, 2017, "App. Br."), the Reply
Brief (filed February 19, 2018, "Reply Br."), the Examiner's Answer
(mailed December 21, 2017, "Ans."), the Final Action (mailed June 22,
Appeal2018-003675
Application 12/963,337
STATEMENT OF THE CASE
The claims relate to a surface mount device containing an RFID
integrated circuit and a matching network. See Abstract.
Invention
Claims 1, 16, 19, and 24 are independent. An understanding of the
invention can be derived from a reading of illustrative claim 1, which is
reproduced below with some formatting added:
1. A device comprising:
a printed circuit board (PCB); and
a surface mount device (SMD) component that is surface
mounted to a surface of the PCB, the SMD component
including a multilayer surface mount structure of dielectric
layers that are laminated together and an RFID (Radio
Frequency Identification) integrated circuit embedded within
the multilayer surface mount structure between dielectric layers
that are laminated together and electrically coupled to a first
end and to a second end of a multilayer inductive coil at
respective pads of the RFID integrated circuit, wherein the
RFID integrated circuit is embedded between a first dielectric
layer that is laminated together to a second dielectric layer, the
multilayer inductive coil including a plurality of traces that are
vertically distributed within the multilayer surface mount
structure between dielectric layers that are laminated together
above and below the embedded RFID integrated circuit and
electrically coupled together vertically by metalized vias to
form the multilayer inductive coil for the RFID integrated
circuit, wherein the plurality of traces above and below the
embedded RFID integrated circuit and the metalized vias form
an uninterrupted conductive path that travels above and below
2017, "Final Act.)," and the Specification (filed December 8, 2010, "Spec.")
for their respective details.
2
Appeal2018-003675
Application 12/963,337
the embedded RFID integrated circuit from the first end to the
second end of the multilayer inductive coil.
Leddige et al.
Ikemoto et al.
References and Rejections
US 2008/0054493 Al
US 2009/0266900 Al
Mar. 6, 2008
Oct. 29, 2009
Claims 1---6, 8, 9, and 16-25 stand rejected under pre-AIA 35 U.S.C.
§ I03(a) as being unpatentable over Ikemoto and Leddige. Final Act. 3-14.
ANALYSIS
We have reviewed the rejection of claims 1-6, 8, 9, and 16-25 m
light of Appellants' arguments that the Examiner erred. We consider
Appellants' arguments seriatim, as they are presented in the Appeal Brief,
pages 6-18.
CLAIMS 1---6, 8, 9, AND 16-25: OBVIOUSNESS OVER IKEMOTO AND LEDDIGE.
Appellants argue all claims as a group over the limitations of Claim 1.
App. Br. 6.
An RFID integrated circuit embedded between dielectric layers.
According to Appellants, claim 1 recites an RFID integrated circuit
that is embedded within a multilayer surface mount structure such that "the
RFID integrated circuit is embedded between a first dielectric layer that is
laminated together to a second dielectric layer" and the traces are "vertically
distributed within the multilayer surface mount structure between dielectric
3
Appeal2018-003675
Application 12/963,337
layers that are laminated together above and below the embedded RFID
integrated circuit." App. Br. 6 ( quoting Claim 1 ).
The Examiner finds Ikemoto teaches an RFID device, substantially as
claimed, except Ikemoto fails to teach the RFID integrated circuit is
embedded between a first dielectric layer that is laminated together to a
second dielectric layer, but the Examiner finds embedding an RFID circuit
between dielectric layers is taught by Leddige. Final Act. 4. In view of
these teachings, the Examiner finds that it would have been obvious:
[T]o modify the surface mount structure of Ikemoto with the
stacked structure of Leddige to provide for an RFID integrated
circuit embedded within a multilayer surface mount structure
wherein the RFID integrated circuit is embedded between a first
dielectric layer that is laminated together to a second dielectric
layer because there are a finite number of layers in a
multilayered structure such that it would have been obvious to
try embedding an integrated circuit on any of the finite layers
for physical protection of the integrated circuit.
Final Act. 5.
Appellants contend Ikemoto ( surface mounting) and Leddige
(stacking) teach two different and incompatible physical structures and the
Examiner has not explained how the combination is "obvious to try." App.
Br. 7. According to Appellants, Leddige teaches a technique for stacking
integrated circuits (ICs):
Many electronic devices require a significant amount of
integrated circuits (IC)s including memory ICs. However,
placing numerous memory ICs directly to a circuit board can
require a relatively large amount of circuit board area. Such a
large circuit board area is often not available in small handheld
electronic devices. Thus, stacking of I Cs on top of each other is
one option for increasing the density of I Cs in small devices.
4
Appeal2018-003675
Application 12/963,337
Also, stacking of I Cs can provide additional benefits, for
example, stacking IC can provide shorter impedance matched
conductors between ICs and this allows for faster clock speeds
and thus faster processing. However, such a configuration
typically requires complex routing strategies for conductors
between ICs in a stack.
App. Br. 8 (quoting Leddige ,r 16). Appellants argue, once having stated the
problem, Leddige proposes a solution: "Accordingly, a stackable die
mounting system with an efficient space saving interconnect is disclosed
herein." Id. ( citing Leddige ,r 17). According to Appellants, Leddige
teaches that IC dies are stacked between base chip carriers which in tum are
separated by [conductive] solder balls, thus are not embedded between two
laminated, dielectric layers. App. Br. 9.
The Examiner finds Ikemoto teaches an RFID integrated circuit atop
laminated layers, but does not explicitly teach embedding the RFID chip
between the laminated layers. Leddige teaches an RFID circuit embedded in
a layered structure or stackable ICs, as the Appellants state. Therefore,
although Ikemoto nor Leddige explicitly teach the claimed limitations, the
combined teachings of Ikemoto and Leddige render obvious the argued
limitation. Ans. 3.
The Examiner finds Appellants' Brief argues Ikemoto and Leddige
are not physically combinable, but the proper test of obviousness is what the
combined teachings of the references would have suggested to those of
ordinary skill in the art. Id. ( citing In re Keller. 3). Thus, the Examiner finds
one of ordinary skill in the art would have recognized the stacked structure
3 In re Keller, 642 F.2d 413 (CCPA 1981).
5
Appeal2018-003675
Application 12/963,337
of Leddige and the layered structure of Ikemoto are analogous and would
have recognized the ability to embed the IC of Ikemoto in the layers of
Ikemoto due to the teaching of Leddige of stacked I Cs. Id. ("Therefore, the
modification does not involve taking the entire stacked structure of Leddige
and locating it between the sheets of Ikemoto, but rather recognizes a
stacked structure of I Cs as a known structure and uses this concept to locate
the IC of Ikemoto in one of the layers of the feeder circuit of Ikemoto."
Ans. 4--5.
Specifically, the Examiner proposes to modify Ikemoto "by taking the
IC that is on top of the stacked feeder structure and locating it within the
layers of the stacked feeder structure. This modification is based on the
combined teaching of Ikemoto and Leddige." Ans. 4. The Examiner finds
"one of ordinary skill in the art would have recognized the stacked nature of
Leddige and the layered structure of Ikemoto as analogous structures and
recognized the ability to embed the IC of Ikemoto in the layers of Ikemoto
due to the teaching of Leddige of stacked I Cs." Ans. 3.
In reply, Appellants contend (1) stacking IC, as taught by Leddige,
does not teach embedding an IC between laminated layers; and, (2) Ikemoto
teaches away from the Examiner's proposed combination ( and the claimed
invention) because Ikemoto teaches the IC should be mounted on top of a
feeder circuit by using existing mounting equipment. Reply Br. 2.
Ikemoto teaches "[t]he wireless IC chip 5 may be mounted on the[]
small feeder circuit substrate 10." Ikemoto ,r 75. Ikemoto teaches this
positioning has the advantage in that a "mounter, or the like, used widely in
the existing art may be used, so mounting cost is greatly reduced." Id.
6
Appeal2018-003675
Application 12/963,337
The Examiner does not explain why a person of ordinary skill in the
art would take Ikemoto's wireless IC, but forego the advantages of top-
mounting, as taught by Ikemoto, to bury the IC between laminated layers, as
taught by Leddige. Appellants point out the disadvantages of Leddige's
stacking: "such a configuration typically requires complex routing strategies
for conductors between ICs in a stack." App. Br. 8 (quoting Leddige ,r 16).
The Examiner does not consider the effect of Leddige' s disadvantages.
We, therefore, decline to sustain the rejection of Claims 1---6, 8, 9, and
16-25.
DECISION
The rejection of Claims 1---6, 8, 9, and 16-25 under 35 U.S.C. § 103 is
REVERSED.
REVERSED
7