Ex Parte Mansell

Board of Patent Appeals and Interferences

Oct 23, 2009

11312653 (B.P.A.I. Oct. 23, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DAVID HENNAH MANSELL
____________

Appeal 2009-008675
Application 11/312,6531
Technology Center 2100
____________

Decided: October 23, 2009
____________

Before JOSEPH L. DIXON, LANCE LEONARD BARRY, and
CAROLYN D. THOMAS, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

I. STATEMENT OF THE CASE

1 Application filed December 21, 2005. The real party in interest is ARM
Limited.
Appeal 2009-008675
Application 11/312,653

2
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection
of claims 1-10, mailed August 22, 2007, which are all the claims pending in
the application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

A. INVENTION
Appellants invented a superscalar data processing apparatus and
method for processing operations. The apparatus having a plurality of
execution threads and each execution thread being operable to process a
sequence of operations including at least one memory access operation. The
superscalar data processing apparatus comprises a plurality of execution
pipelines for executing the operations, and issue logic for allocating each
operation to one of the execution pipelines for execution by the execution
pipeline. (Spec. 22, see Abstract.)

B. ILLUSTRATIVE CLAIM
The appeal contains claims 1-10. Claims 1 and 10 are independent
claims. Claim 1 is illustrative:
1. A superscalar data processing apparatus having a
plurality of execution threads, each execution thread being operable to
process a sequence of operations including at least one memory access
operation, the superscalar data processing apparatus comprising:
a plurality of execution pipelines operable to execute the
operations;
issue logic operable to allocate each operation to one of
said execution pipelines for execution by that execution pipeline;
at least two of said execution pipelines being memory
access capable pipelines which are capable of executing memory
Appeal 2009-008675
Application 11/312,653

3
access operations, each memory access capable pipeline being
associated with only a subset of said plurality of execution threads for
the purpose of executing memory access operations, said subset is less
than all of said plurality of execution threads;
the issue logic being operable, for each execution thread,
to allocate any memory access operations of an execution thread to an
associated memory access capable pipeline.

C. REFERENCES
The references relied upon by the Examiner as evidence in rejecting
the claims on appeal are as follows:
Nemirovsky US 7,035,998 B1 Apr. 25, 2006
Bishop US 2006/0179346 A1 Aug. 10, 2006

D. REJECTION
The Examiner entered the following rejection which is before us for
review:
Claims 1-10 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Bishop in view of Nemirovsky.

II. FINDINGS OF FACT
The following findings of fact (FF) are supported by a preponderance
of the evidence.
Bishop
1. Bishop discloses that “[p]rocessor 200 comprises a single integrated
circuit superscalar microprocessor with dual-thread SMT.” (¶ [0040].)
2. Bishop discloses “load/store units (LSUA) 207a and (LSUB) 207b
. . . Execution units . . . 207a, 207b, . . . are fully shared across both
threads.” (¶ [0042].)
Appeal 2009-008675
Application 11/312,653

4
III. PRINCIPLES OF LAW
“What matters is the objective reach of the claim. If the claim extends
to what is obvious, it is invalid under § 103.” KSR Int’l Co. v. Teleflex, Inc.,
550 U.S. 398, 419 (2007). To be nonobvious, an improvement must be
“more than the predictable use of prior art elements according to their
established functions.” Id. at 417.
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)). Therefore, we look to Appellants’ Brief to show error in
the proffered prima facie case. Only those arguments actually made by
Appellants have been considered in this decision. Arguments which
Appellants could have made but chose not to make in the Brief has not been
considered and are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii).

IV. ANALYSIS
Common Feature In All Claims
Our representative claim, claim 1 recites, inter alia, “each memory
access capable pipeline being associated with only a subset of said plurality
of execution threads . . . said subset is less than all of said plurality of
execution threads.” Independent claim 10 recites essentially the same
limitation.

Appeal 2009-008675
Application 11/312,653

5
The Obviousness Rejection
We now consider the Examiner’s rejection of the claims under
35 U.S.C. § 103(a).
Appellant contends that the “Examiner has failed to indicate where
Bishop discloses that each MAC pipeline is ‘associated with only a subset of
said plurality of execution threads’ as recited in independent claims 1 and
10.” (App. Br. 9.)
The Examiner found that “because only one memory access operation,
at a time (or at one clock cycle[)] (Bishop, paragraph [0046] and [0054]),
can be dispatch[ed] to element 207a, element 207a is a subset (Thread 0) of
said plurality of execution threads (thread 0 and thread 1). Also, this can be
the case for thread 1, dispatching to element 207a at a time (or at one clock
cycle as explained above.)” (Ans. 6.)

Issue: Has Appellant shown that the Examiner erred in finding that
the Bishop discloses that each memory access capable pipeline being
associated with only a subset of the plurality of execution threads for the
purpose of executing memory access operations?

Claim 1 recites, inter alia, that “each memory access capable pipeline
being associated with only a subset of said plurality of execution threads, . . .
said subset is less than all of said plurality of execution threads.” A broad
but reasonable interpretation of “being associated with” involves having
some type of relationship with. Here, claim 1 requires that “less than all” of
the threads can have a relationship with any particular memory access
capable pipeline. It does not matter during what timeframe, i.e., at the same
Appeal 2009-008675
Application 11/312,653

6
time or not. What is required is that less than all of the threads can utilize a
particular memory capable pipeline.
Nemirovsky is not being relied upon to show this feature, instead, the
Examiner found that the above noted claim limitation reads on Bishop’s
disclosure of each thread performing only one memory access operation at a
time (Ans. 6). However, we find that the Examiner’s findings merely point
to a temporal distinction rather than an association, as required by the
claims. As such, we disagree that Bishop discloses the above-noted
limitation.
For example, Bishop discloses a dual thread configuration having two
load/store units (e.g., memory access capable pipelines) (FF 1-2). Bishop
further discloses that the load/store units are fully shared across both threads
(FF 2). In other words, all of Bishop’s threads have a relationship with, i.e.,
are associated with, the memory access capable pipelines.
Since we agree with at least one of the arguments advanced by
Appellant, we need not reach the merits of Appellant’s other arguments. It
follows that Appellant has shown that the Examiner erred in finding the
combination of Bishop and Nemirovsky renders claims 1-10 unpatentable.
Thus, Appellant has persuaded us of error in the Examiner’s
conclusion of obviousness for representative claim 1. Therefore, we reverse
the Examiner’s § 103 rejection of independent claim 1 and of claims 2-10,
which stand therewith.

V. CONCLUSION
We conclude that Appellant has shown that the Examiner erred in
rejecting claims 1-10.
Appeal 2009-008675
Application 11/312,653

7

VI. DECISION
In view of the foregoing discussion, we reverse the Examiner’s
rejection of claims 1-10.

REVERSED

Erc

NIXON & VANDERHYE, PC
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203