Ex Parte Mamidwar et al

Patent Trial and Appeal Board

Mar 12, 2013

10832750 (P.T.A.B. Mar. 12, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________
Ex parte RAJESH MAMIDWAR and IUE-SHUENN CHEN
____________________

Appeal 2010-008612
Application 10/832,750
Technology Center 2100
____________________

Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and
CARLA M. KRIVAK, Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL

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Application 10/832,750

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 2-16, 18, 19, 21-36, and 38-42. Claims 1, 17, 20, and 37 were
canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

INVENTION
Appellants’ claimed invention is generally related to the collection
and processing of incoming data streams from serial communication
channels. More specifically, the invention is a method and system for a
merged rate-smoothing buffer with a burst buffer. (Spec. 1).
Independent claim 40, reproduced below, is representative of the
subject matter on appeal.
40. A method for processing data streams, the method
comprising:

processing at least one of a plurality of data blocks
comprising data having a plurality of data rates;

transferring said processed at least one of a plurality of
data blocks into at least one of a plurality of buffer slots in a
single data buffer, wherein said plurality of buffer slots in said
single data buffer are controlled by a data buffer controller, and
said data buffer controller utilizes said plurality of buffer slots
in said single data buffer to handle both:

rate-smoothing of said transferred at least one of a
plurality of data blocks comprising data having said
plurality of data rates; and

buffering and assembling of said transferred at
least one of a plurality of data blocks for bursting;

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selecting at least one of said transferred processed at least
one of a plurality of data blocks from said at least one of a
plurality of buffer slots in said single data buffer; and

transferring a data block burst from at least a portion of
said selected transferred processed at least one of a plurality of
data blocks.

REFERENCES
Hu US 4,736,317 Apr. 5, 1988
Munter US 5,475,679 Dec. 12, 1995
Hauser US 5,748,905 May 5, 1998
Ahmed US Pat. App. Pub. No.: 2003/0188247 A1 Oct. 2, 2003
Porter US Pat. App. Pub. No.: 2003/0226029 A1 Dec. 4, 2003
Parry US Pat. App. Pub. No.: 2004/0117534 A1 Jun. 17, 2004
Filed Dec. 13, 2002
Emmot US 6,842,179 B2 Jan. 11, 2005
Filed Feb. 20, 2002
Segal US 6,859,434 B2 Feb. 22, 2005
Filed Oct. 1, 2002
Appellants’ Admitted Prior Art (APA)

REJECTIONS
Claims 2, 3, 15, 16, 18, 19, 21, 22, 34, 36, 38, 39, and 40-43 stand
rejected under 35 U.S.C. § 103(a) as being unpatentable over APA and
Munter.
Claims 4 and 23 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over APA, Munter, and Ahmed.
Claims 5-7 and 24-26 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over APA, Munter, and Porter.
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Claims 8, 9, and 27 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over APA, Munter, Porter, and Segal.
Claims 10, 28, and 29 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over APA, Munter, and Hauser.
Claims 11, 12, 30, and 31 stand rejected under 35 U.S.C. §103(a) as
being unpatentable over APA, Munter, and Parry.
Claims 13 and 14 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over APA, Munter, and Hu.
Claims 32 and 33stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over APA, Munter, Parry, and Hu.
Claim 35 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over APA, Munter, and Emmot.

ANALYSIS
With respect to independent claims 40-42, Appellants set forth
arguments for patentability for the group. Therefore, we select independent
claim 40 as the representative claim for the group and will address
Appellants' arguments thereto.
Appellants' principal contention is that neither the APA nor the
teachings of the Munter reference describes, teaches, or suggests the
claimed:
a single data buffer, wherein said plurality of buffer slots in said
single data buffer are controlled by a data buffer controller, and
said data buffer controller utilizes said plurality of buffer slots
in said single data buffer to handle both: rate-smoothing of said
transferred at least one of a plurality of data blocks comprising
data having said plurality of data rates; and buffering and
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assembling of said transferred at least one of a plurality of data
blocks for bursting.

(App. Br. 10; Reply Br. 3, emphasis omitted). Appellants contend that the
APA teaches separate and distinct input and output buffers. (App. Br. 11-
12). Appellants additionally contend that contrary to the Examiner's
suggestion, the claims recite more than just "making two data buffers into a
single data buffer." (App. Br. 15). As the present application explains, the
prior art, i.e., the APA, used multiple buffers for rate smoothing and burst
buffering. (Spec. 2, ll. 1-20). (App. Br. 15). Appellants further contend that
the single data buffer produces a smaller chip area, increased processing
speed, and reduced manufacturing costs. (Spec. 15, ll. 4-6) (App. Br. 15).
While we agree with Appellants as to the proffered benefits of the single
data buffer, we agree with the Examiner that the Munter reference teaches or
fairly suggests the use of a single memory buffer, as discussed
infra.Therefore, Appellants' argument does not show error in the Examiner's
reasoned conclusion of obviousness.
Appellants identify the relied upon teaching of column 4, lines 30-39,
as disclosing a single data buffer. (App. Br. 12-13). Appellants further
contend that Figures 1-3 of the Munter reference disclose a plurality of
buffers. While we agree with Appellants that Munter’s Figures 1-3 show
plural "buffer modules," we disagree that the "buffer modules" necessarily
correlate to plural "buffers." Rather, we find a difference in the terminology
between the claimed invention and the disclosure of the Munter reference.
The Examiner relies upon that description in the Munter reference that
recites "ordinarily an input buffer module and an output buffer module are
located at a port and therefore the cell RAM at each buffer module can be
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made of a single memory with a time divided buffer control circuit serving
both functions." (Munter col. 4, ll. 35-39) (Ans. 13). The Examiner
additionally identifies Munter’s Figures 3, 4, and 7 to support the contention
that the Munter reference teaches a single memory for plural buffer modules.
(Ans. 15). We agree with the Examiner.
Appellants identify the same quotation, but the draw a different
conclusion than the Examiner. (App. Br. 13-14). We disagree with
Appellants' conclusion and find that the time divided buffer control circuit
serving both functions of input and output with respect to the single memory
medium supports the Examiner’s finding that the Munter reference teaches
and fairly suggests an input data buffer module and an output data buffer
module being on a single RAM/memory. Therefore, the two data buffer
modules would form a single data buffer. We find no additional limitations
expressly recited in the language of independent claim 40 which distinguish
the claimed “transferring said processed at least one of a plurality of data
blocks into at least one of a plurality of buffer slots in a single data buffer”
or a single buffer memory with two data "buffer modules" performing two
separate functions (input and output). Thus, these claimed features are
clearly taught and suggested in the APA.
With respect to dependent claims 4 and 23, Appellants contend that
the Ahmed referenced teaches padding, but the language of representative
claim 4 recites "masking." (App. Br. 15). Appellants contend that
"[p]adding is not the same as masking." (App. Br. 15). Appellants contend
that "data masking relates to when specific symbol(s) of a data are replaced
by other symbol(s)." (App. Br. 15). Appellants do not identify any support
from their Specification or otherwise for this contention.
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The Examiner addresses this argument with respect to "claim 3 [sic,
4]." (Ans. 16-17). We note that Appellants' Specification states that "[i]f
the data block burst has fewer data blocks than required by the burst length
parameter, the output controller 208 may mask or pad the data block burst in
step 322 to meet the burst length parameter." (Spec. [34], emphasis added).
Since Appellants' Specification identifies either masking or padding may be
used to meet the length parameter, we find Appellants' argument
unpersuasive of error in the Examiner's conclusion of obviousness of
representative claim 4.
With respect to dependent claims 8, 9, and 27, Appellants argue these
claims as a group. (App. Br. 16-17). Therefore, we select dependent claim
8 as the representative claim for the group and will address Appellants'
arguments thereto. The Examiner addresses this argument with respect to
"claim 5 [sic, 8]" which discusses the Segal reference. (Ans. 17-18).
Appellants argue that the Segal reference does not describe, teach, or suggest
such a selection before processing. We disagree with Appellants and find
the Segal references discloses configurable switching is performed prior to
any processing and therefore teaches and fairly suggests selecting at least
one of a plurality of incoming data streams if said storing before said
processing was selected, since Segal discloses selecting, buffering, and
processing in that order. Therefore, Appellants' argument does not show
error in the Examiner's legal conclusion of obviousness.
With respect to claims 10-12 and 28-31, Appellants rely on the prior
arguments. (App. Br. 17). Since we found error in Appellants’ arguments
with respect to Appellants’ parent claims, we similarly find error in
Appellants' general arguments.
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With respect to dependent claims 13 and 14, Appellants present a
single argument to these claims. (App. Br. 17-18). Therefore, we select
claim 13 as the representative claim for the group and will address
Appellants' arguments thereto. Appellants merely contend that the stack
pointer of the Hu reference does not generate a notification. We disagree
with Appellants’ general contention and find that a stack pointer is a
notification for storage of the data. Therefore, Appellants' argument does
not show error in the Examiner's conclusion of obviousness.
With respect to dependent claims 16, 35, and 36, Appellants rely on
the prior arguments which we found unpersuasive. Therefore, we sustain the
rejection of claims 16, 35, and 36.
With respect to dependent claims 32 and 33, Appellants set forth the
same argument advanced with respect to claims 13 and 14 (App. Br. 18-19),
which we found unpersuasive of error in the Examiner's conclusion of
obviousness.
Appellants' Reply Brief sets forth similar arguments and maintains the
Examiner's rejections are conclusory and not supported. (Reply Br. 2-6).
We disagree with Appellants' contentions and find the Examiner's rejection
sufficient to support a conclusion of obviousness.

CONCLUSION
The Examiner did not err in rejecting claims 2-16, 18-29, 21-36, and
38-42 under 35 U.S.C. § 103(a).

Appeal 2010-008612
Application 10/832,750

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DECISION
The Examiner’s decision rejecting claims 2-16, 18-29, 21-36, and 38-
42 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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