Ex Parte MacInnis et al

Patent Trial and Appeal Board

Nov 18, 2014

10763087 (P.T.A.B. Nov. 18, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte ALEXANDER G. MACINNIS, CHENGFUH JEFFREY TANG,
XIAODONG XIE, JAMES T. PATTERSON, and GREG A.
KRANAWETTER
____________

Appeal 2012-006921
Application 10/763,087
Technology Center 2100
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Before CARL W. WHITEHEAD JR., JOHNNY A. KUMAR, and BETH Z.
SHAW, Administrative Patent Judges.

SHAW, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 4, 5, 7–10, and 12, which constitute all the claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b).
Claims 1–3, 6, and 11 are cancelled. (App. Br. Claims App’x.)
We reverse.

Appeal 2012-006921
Application 10/763,087

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STATEMENT OF THE CASE
Appellants’ disclosed invention relates to an integrated circuit
graphics display system (Spec. 2:7–10.) Independent claim 4, which is
illustrative, reads as follows:
4. A unified memory system comprising:
a memory that is shared by a plurality of devices
including at least a central processing unit and a graphics
processing unit;
a memory request arbiter coupled to the memory,
wherein the memory request arbiter performs real time
scheduling of memory requests from different devices having
different priorities, the unified memory system provides for real
time scheduling of tasks, and provides access to memory by
requesters that are sensitive to latency and do not have
determinable periodic behavior;
dual memory controllers, the dual memory controllers
including a first memory controller and a second memory
controller, the memory request arbiter including a first arbiter
coupled to the first memory controller and a second arbiter
coupled to the second memory controller, wherein the first
arbiter and the second arbiter perform real time scheduling of
memory requests, wherein memory requests to the memory
shared by the plurality of devices are routed to a particular one
of the first arbiter and the second arbiter based on the address of
the memory request; and
a memory select circuit receiving requests from the
central processing unit and graphics processing unit, selecting
one of the dual memory controllers and one of the first arbiter
or second arbiter, and providing the request to the selected one
of the dual memory controllers and the selected one of the first
arbiter or second arbiter; and
wherein a predetermined minimum interval between
subsequent accesses by a device is enforced, and wherein said
predetermined minimum interval is long enough for another
device to access.
Appeal 2012-006921
Application 10/763,087

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Claims 4, 5, 7–10, and 12 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Ben-Yoseph et al. (US 5,949,439; Sept. 7, 1999;
hereinafter “Ben”), Robinett et al. (US 6,351,474 B1; Feb. 26, 2002;
hereinafter “Robinett”), and Ottinger (US 6,070, 231; May 30, 2000). (Ans.
4–10.)

ISSUES
We have reviewed Appellants’ arguments and contentions in light of
the Examiner’s findings (Ans. 4–8) and explanations (Ans. 8–12) regarding
independent claim 4. The dispositive issue is: Did the Examiner err in
finding the combination Ben, Robinett, and Ottinger teaches or suggests
“wherein memory requests to the memory shared by the plurality of devices
are routed to a particular one of the first arbiter and the second arbiter based
on the address of the memory request,” as recited in claim 4?

ANALYSIS
We find Appellants’ arguments persuasive and agree the Examiner
erred in finding the combination Ben, Robinett, and Ottinger teaches or
suggests “wherein memory requests to the memory shared by the plurality of
devices are routed to a particular one of the first arbiter and the second
arbiter based on the address of the memory request,” as recited in claim 4
(See App. Br. 7-10). In the Final Rejection and the Grounds of Rejection,
the Examiner cites Ottinger’s Figure 2 (Ans. 6) as teaching this limitation.
For the first time in the Answer, the Examiner also cites to column 16, lines
20 and 21 of Ottinger (Ans. 12) as teaching this limitation. In the Answer,
the Examiner contends Ottinger describes that “the first and second arbiter
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Application 10/763,087

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BOTH follow the same address based routing arbitration scheme” (Ans. 12).
We do not find such a disclosure in the cited portions of Ottinger; nor do we
see how such a disclosure, even if found in Ottinger, would teach or suggest
the “memory requests to the memory shared by the plurality of devices are
routed to a particular one of the first arbiter and the second arbiter based on
the address of the memory request,” as recited in claim 4 (emphasis added).
Because we are persuaded of error with regard to this issue, which is
dispositive of the rejection of claim 4 over Ben, Robinett, and Ottinger, we
do not address the additional arguments raised by Appellants.
Accordingly, we do not sustain the rejection of claim 4, or claims 5,
7–10, or 12, which depend, directly or indirectly, from claim 4.
DECISION
The decision of the Examiner to reject claims 4, 5, 7–10, and 12 is
reversed.

REVERSED

lv