11269424 (P.T.A.B. Oct. 25, 2012)

Ex Parte MacInnis et al

Patent Trial and Appeal BoardOct 25, 2012

11269424 (P.T.A.B. Oct. 25, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte ALEXANDER G. MACINNIS, VIVIAN HSIUN, SHENG ZHONG, XIAODONG XIE, KIMMING SO, and JOSE R. ALVAREZ ____________ Appeal 2011-006093 Application 11/269,424 Technology Center 2400 ____________ Before JOSEPH L. DIXON, MARC S. HOFF, and GREGORY J. GONSALVES, Administrative Patent Judges. GONSALVES, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-006093 Application 11/269,424 2 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of claims 1-4, 7-15, 19-21, and 27-31 (App. Br. 2). Claims 5, 6, 16-18, and 22- 26 were cancelled (id.). We have jurisdiction under 35 U.S.C. § 6(b). We affirm. The Invention Exemplary Claim 1 follows: 1. A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface; and an entropy decoding accelerator coupled to the co- processor interface of the core decoder processor, wherein the entropy decoding accelerator is adapted to receive commands from the core decoder processor via the co-processor interface and to perform entropy decoding operations on entropy-coded code in the data stream in response to said commands. Claims 1-4, 7-15, 19-21, and 27-31 stand rejected under 35 U.S.C. § 102(e) as being anticipated by Kono (U.S. 6,628,719) (Ans. 3-9). Claims 1-4, 7-15, 19-21, and 27-31stand rejected under 35 U.S.C. § 102(e) as being anticipated by Sullivan (U.S. 6,891,893) (Ans. 11-16). FACTUAL FINDINGS We adopt the Examiner’s factual findings as set forth in the Answer (Ans. 3, et seq.). Appeal 2011-006093 Application 11/269,424 3 ISSUE Appellants’ responses to the Examiner’s positions present the following issue: Did the Examiner err in finding that Sullivan discloses “a core decoder processor . . . having a co-processor interface; and an entropy decoding accelerator coupled to the co-processor interface of the core decoder processor,” as recited in independent claim 1 and as similarly recited in independent claims 9 and 19? ANALYSIS We disagree with Appellants’ assertions regarding the Examiner’s anticipation rejections of claims 1-4, 7-15, 19-21, and 27-31. We adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken and (2) the reasons set forth by the Examiner in the Answer in response to arguments made in Appellants’ Appeal Brief and Reply Brief. We concur with the conclusion reached by the Examiner. We highlight and address certain findings and arguments below. Appellants contend that the Examiner erred in rejecting independent claim 1 as anticipated because Sullivan does not disclose “a core decoder processor . . . having a co-processor interface,” (App. Br. 5). Appellants also contend that Sullivan does not disclose “an entropy decoding accelerator coupled to the co-processor interface of the core decoder processor” (id. at 6). In support of their contentions, Appellants argue that the “multimedia accelerator 174 [of Sullivan] are not coupled to the host processor 132 of Sullivan via a co-processor interface” (id. at 7). Appeal 2011-006093 Application 11/269,424 4 The Examiner found, however, that Sullivan discloses a co-processor interface as an “application program interface (API) . . . to characterize the processing capability of one or more communicatively coupled multimedia accelerators” (Ans. 16). We agree with the Examiner. Our reviewing Court requires us to give a claim its broadest reasonable meaning consistent with the Specification. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). Appellants’ Specification shows a co-processor interface as an interface between a core processor 302 and a VLD (variable length decoder) 306 (FIG. 5, ¶¶ [72]-[74]). Similarly, Sullivan discloses a host processor and multimedia accelerators that perform “decoding of multimedia content” (col. 4, ll. 4-5) and an API (104) between the host processor 132 and multimedia accelerators 174A-174N (FIG. 2). Accordingly, under the proper claim construction, Sullivan’s disclosure of an interface between a host processor and multimedia accelerators qualifies as the claimed co-processor interface. Thus, we find no error in the Examiner’s rejection of claim 1 as anticipated by Sullivan. Appellants also argue that the Examiner erred in rejecting claim 9 as anticipated because Sullivan does not disclose “(a) providing a command to the accelerator via a posted write operation; and (b) polling the accelerator to determine whether an operation corresponding to the command has been performed” (App. Br. 7). But the Examiner found that Sullivan meets this claim limitation because it discloses that a host processor sends commands to multimedia accelerators by writing or posting them in a data structure and determines whether the commands were performed (Ans. 17-18). We agree with the Examiner. Sullivan discloses the posting of commands in Auto- Negotiation Data Structures at the interface between the Host Processor 132 Appeal 2011-006093 Application 11/269,424 5 and the Multimedia Accelerators 174A-N (FIG. 2). Sullivan also discloses that a decoder 160 executes on the host processor 132 and that in response to the commands issued at the host processor, “data is returned to the decoder 160 in the form of … the read-back command buffer” (col. 25, ll. 20-21). Accordingly, we find no error in the Examiner’s rejection of independent claim 9 as anticipated by Sullivan. Appellants also contend that the Examiner erred in rejecting claim 19 as anticipated because Sullivan does not disclose that the “decoding accelerator is adapted to provide status data indicative of a status of the first accelerator to the co-processor status register” (App. Br. 9). In support of their contention, Appellants argue that the multimedia accelerators of Sullivan “do not provide status data indicative of a status of the accelerator to the host processor 132” (id.) The Examiner found, however, that Sullivan meets this claim limitation because it discloses operational data structures that contain status information from the accelerators (Ans. 20). We agree with the Examiner. Sullivan discloses “operational data structure(s) . . . to facilitate the communication required to effect the negotiated division in media decoding among and between media processing system elements (e.g., decoder application and accelerator)” (col. 12, ll. 4-9). Accordingly, we find no error in the Examiner’s rejection of claim 19 as anticipated by Sullivan. We also find no error in the Examiner’s rejection of the remaining claims on appeal (i.e., claims 2-4, 7, 8, 10-15, 20, 21, and 27-31) as Appeal 2011-006093 Application 11/269,424 6 anticipated by Sullivan because Appellants did not set forth any separate patentability arguments for those claims (see App. Br. 5-10).1 DECISION We affirm the Examiner’s decision rejecting claims 1-4, 7-15, 19-21, and 27-31 as anticipated by Sullivan. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED peb 1 Because we affirm the Examiner’s decision rejecting all of the claims on appeal as anticipated by Sullivan, we find it unnecessary to review the Examiner’s anticipation rejections with respect to Kono.