Ex Parte Lu et al

Patent Trial and Appeal Board

Aug 30, 2016

13356173 (P.T.A.B. Aug. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/356, 173 01/23/2012
43859 7590 09/01/2016
SLATER MATSIL, LLP
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252
FIRST NAMED INVENTOR
Szu Wei Lu
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TSMll-1127 8369
EXAMINER
GONDARENKO, NATALIA A
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
09/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@slatermatsil.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SZU WEI LU, YING-DA WANG, LI-CHUNG KUO,
and JING-CHENG LIN
Appeal2015-003963
Application 13/356, 173
Technology Center 2800
Before LINDA M, GAUDETTE, MICHELLE N. ANKENBRAND, and
LILAN REN, Administrative Patent Judges.
GAUDETTE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2015-003963
Application 13/356,173
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's decision2
finally rejecting claims 1-3, 5-8, 10-13, and 21-28. We have jurisdiction under
35 U.S.C. § 6(b).
We REVERSE.
The invention is directed to a method that reduces the problem of warpage of
an interposer wafer that occurs during the manufacture of an integrated circuit
package. See Specification filed January 23, 2012 ("Spec."), i-fi-f l-2. According to
the Specification, a known method of packaging integrated circuits includes steps
of bonding a plurality of dies on an interposer wafer, dispensing an underfill into
the gaps between the dies and the interposer wafer, and curing. Id. i-f l. A
drawback of this method is that the underfill may shrink after being cured and
apply a force on the dies and the interposer wafer, causing the interposer wafer to
warp. Id. i12. The inventors are said to have discovered that this problem can be
alleviated by sawing portions of the underfill to create a trench between
neighboring dies after the underfill is cured. See id. i-fi-f 15-16. The trench
subsequently is filled with a second polymer. Id. i-f 18. Claims 1 and 8 are
representative of the inventive method, and read as follows:
1. A method comprising:
bonding a first and a second package component on a top
surface of a third package component;
dispensing a first polymer, wherein the first polymer comprises:
a first portion in a space between the first and the third package
components;
a second portion in a space between the second and the third
package components; and
1 Appellants identify the real party in interest as Taiwan Semiconductor
Manufacturing Co., Ltd. Appeal Brief filed October 8, 2014 ("App. Br."), 3.
2 Final Office Action mailed April 9, 2014 ("Final Act.").
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Appeal2015-003963
Application 13/356,173
a third portion in a gap between the first and the second
package components;
performing a curing on the first polymer;
after the curing, sawing the third portion of the first polymer to
form a trench between the first and the second package components,
wherein the trench has a bottom higher than a top surface of the third
package component; and
after the step of sawing, molding the first, the second, and the
third package components with a second polymer, wherein the second
polymer is filled into the trench.
8. A method comprising:
bonding a first die, a second die, and a third die onto a top
surface of a wafer, wherein the first die is immediately neighboring
the second die and the third die, with no additional dies therebetween,
and wherein the second die is between the first die and the third die;
dispensing an underfill to spaces between the first and the
second dies and the wafer, wherein the underfill comprises a portion
disposed in a gap between the first and the second dies, and wherein
the underfill is not filled into a space between the second die and the
third die;
performing a curing step to cure the underfill;
after the curing step, sawing the portion of the underfill to form
a trench; and
after the step of sawing, performing a thermal step to anneal the
underfill, wherein after the curing step, the underfill is partially cured.
The Examiner maintains the following grounds of rejection under 35 U.S.C.
§ 103(a)3:
1. Claims 1, 5, 7, 22, 23, and 28 are rejected as unpatentable over Saito
et al. (U.S. Patent No. 6,794,273 B2, issued Sept. 21, 2004 ("Saito")) in view of
3 The Examiner has withdrawn the rejection of claims 5, 22-24, and 27 under
35 U.S.C. § 112, second paragraph. Examiner's Answer mailed December 20,
2014 ("Ans."), 2.
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Appeal2015-003963
Application 13/356,173
Mariani et al. (U.S. Publication No. 2009/0189258 Al, published July 30, 2009
("Mariani")).
a. Claims 2 and 3 are rejected as unpatentable over Saito in view
of Mariani, further in view of Patwardhan et al. (U.S. Patent No. 7,413,927
B 1, issued Aug. 19, 2008 ("Patwardhan") ).
b. Claims 2, 6, and 24 are rejected as unpatentable over Saito in
view of Mariani, further in view of Scheifers et al. (U.S. Patent No.
6,562,663 B2, issued May 13, 2003 ("Scheifers")).
c. Claims 6 and 24 are rejected as unpatentable over Saito in view
of Mariani, further in view of Farnworth et al. (U.S. Patent No.7,157,353
B2, issued Jan. 2, 2007 ("Farnworth")).
c. Claims 25 and 27 are rejected as unpatentable over Saito in
view of Mariani, further in view of Chung (U.S. Publication No.
2009/0001602 Al, published Jan. 1, 2009 ("Chung")).
2. Claims 8, 10-13, and 21 are rejected as unpatentable over Saito in
view of Mariani, Patwardhan, and Pogge et al. (U.S. Patent No. 6,066,513, issued
May 23, 2000 ("Pogge")).
a. Claim 26 is rejected under 35 U.S.C. § 103(a) as unpatentable
over Saito in view of Mariani, Patwardhan, and Pogge, further in view of
Chung.
3. Claims 8 and 10-13 are rejected as unpatentable over Saito in view of
Meyer et al. (U.S. Publication No. 2011/0241218 Al, published Oct. 6, 2011
("Meyer")), Patwardhan, and Pogge.
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Appeal2015-003963
Application I3/356,I 73
Claim 1
Claim I recites: "sawing the third portion of the first polymer to form a
trench between the first and the second package components, wherein the trench
has a bottom higher than a top surface of the third package component ... wherein
[a] second polymer is filled into the trench" (emphasis added).
Saito describes a method of making a stacked structure (interposer) on
silicon wafer I, as illustrated in Figure IF, below. See Saito 6:36-37, I0:33-37.
FIG.1 F
As shown in Figure IF, the interposer includes insulating layers 5, 9, IO,
lands I I, and internally formed capacitors 8 (not labelled) embedded in insulating
layer 9. Id. at 9:32-33, 9:48--49, 9:58, I0:2-9. The interposer is mounted on
silicon wafer I by means of an adhesive, peelable resin layer 3 and adhesive resin
layer 2. See id. at 8:42-55. Resin layer 2 has a grid configuration corresponding
to dicing lines for a subsequent dicing step. Id. at 9:35-36.
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Appeal2015-003963
Application 13/356,173
The Examiner finds Saito, in the embodiments of Figures 4A---C, 6A---C, and
37--42, describes the claim 1 steps of bonding package components, dispensing a
first polymer in first/second/third portions, curing the first polymer, and sawing the
third portion of the first polymer. See Final Act. 4--5. In the Answer, the
Examiner provides a marked-up copy of Saito Figures 6A---C, reproduced below,
identifying each of these steps. Ans. 3.
Figures 6A---C are diagrams showing the steps in a method of manufacturing
a semiconductor device using an interposer. Saito 6:51-54. According to the
method, semiconductor chips 31 are mounted on interposer 30 adhered to silicon
wafer 1, the interposer and wafer being described above in connection with Figure
l>'l';mfaig
p<1dt:~g>I." >;;Qttii»IWtlt~
dk>ptHl~fa~1 f,<0-1~'>-,.~I" ,, '~
IF. Id. at 11 :40--42. Semiconductor chips 31 are sealed using sealing resin 32,
forming a plurality of semiconductor devices 33 on silicon wafer 1. Id. at 11 :55-
59. UV tape 34 is attached to the back surface of silicon wafer 1, and a step of
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Appeal2015-003963
Application 13/356,173
individualizing semiconductor devices 33 is performed using dicing blade 12. Id.
at 11: 59---62. Saito discloses that "[ t ]he cuts made by the dicing blade 12 have a
depth such that the dicing blade slightly goes into the silicon wafer 1 but the silicon
wafer 1 is not separated by the cuts." Id. at 11 :63---65. "[T]he resin layer 3 is also
individualized by the individualizing step, [so that] semiconductor devices 33 can
be easily peeled off from the silicon wafer 1 that remains unindividualized (in one
piece)." Id. at 12:5-8.
The Examiner finds Saito's two adjacent semiconductor chips 31 meet the
claim 1 limitation of "a first and a second package component" and the
combination of interposer 30 adhered to silicon wafer 1 meets the limitation of "a
third package component." Final Act. 4. The Examiner finds the "third portion"
of the "first polymer," as recited in claim 1, reads on the portion of sealing resin 32
between semiconductor chips 31. Id. at 5. The Examiner finds Saito does not
disclose sawing sealing resin 32 to form a trench between semiconductor chips 31,
filling the trench with a second polymer, and then molding as recited in claim 1.
Id. The Examiner finds, however, that one of ordinary skill in the art would have
been motivated to modify Saito' s method by forming a trench between
semiconductor chips 31 and filling the trench with a coating prior to Saito' s step of
individualizing semiconductor devices 33 (see Saito 11 :59---62) based on Mariani's
teaching of "an improved semiconductor wafer dicing or singulating process"
(Mariani i-f 4) that includes such steps of forming and filling a trench. See Final
Act. 5---6.
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Appeal2015-003963
Application 13/356,173
Figure 6 of Mariani is reproduced below.
Figure 6 is a perspective view of a portion of semiconductor wafer 30.
Mariani i-f 12. Wafer 30 includes layer 31 (e.g., silicon), having a plurality of
integrated circuits 34 in front surface 32, and metal layer 36, deposited on the rear
surface (i.e., the surface opposite front surface 32). Id. i-fi-134, 36. Mariani
describes forming trenches 60, 64 having width W 1 and depth D 1 in the rear
surface along lines corresponding to dicing lines 40 scribed on front surface 32
between individual integrated circuits 34. Id. i-f 37; see Fig. 4. "Dicing lines 40
indicate the lines along which wafer 30 will be diced or singulated to form
individual semiconductor chips." Id. i-f 34. After formation of trenches 60, 64,
layer 70 is applied to cover the rear surface of wafer 30 and to fill trenches 60, 64.
Id. i-f 39. Trenches 74, 78 having width W2 and depth D2 are formed thereafter in
front side 32 along dicing lines 40, in alignment with trenches 60, 64, respectively.
Id. i-f 40.
Mariani Figure 22, below, is a cross-sectional view of wafer 130, formed
using a method similar to that described in connection with Figure 6, but including
an additional step of filling trenches 178 in front side 132 with a material that is the
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Appeal2015-003963
Application 13/356,173
same as coating 170 that fills trenches 164 on the rear surface. Id. il 61; see also
Fig. 21.
As illustrated in Figure 22, trenches 178 have a width less than that of
trenches 164, and a depth that extends into coating 170 in trenches 164 but not
beyond the rear surface of wafer 130. Id.; see also Fig. 21. Dicing blade 186 is
aligned with trenches 164, 178 and used to cut completely through coating 170 and
separate or singulate semiconductor chip 190 from wafer 130. Id. According to
l\1ariani, the inventive method is an improvement over prior art dicing or
singulating processes in which a dicing blade saws or grinds the wafer and metal
layer between the individual integrated circuits "creat[ing] defects, such as
cracking and chipping of the semiconductor material along the cut edges proximate
to the rear side of the wafer, and chipping, cracking, and burring along the cut
edges of the metal layer." Id. i-fi-12, 4.
Appellants contend the Examiner reversibly erred in finding one of ordinary
skill in the art would have been motivated to modify Saito' s method, based on the
teachings of Mariani, to form a trench in Saito's sealing resin 32 between
semiconductor chips 31 (i.e., the third portion of the first polymer between the first
and second package components) such that "the trench has a bottom higher than a
top surface of the third package component" (claim 1 ), i.e., the surface of
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Appeal2015-003963
Application 13/356,173
interposer 30 on which semiconductor chips 31 are mounted. Reply Br. 7; see also
App. Br. 16-17. Appellants argue Mariani forms a trench to facilitate dicing a
wafer (App. Br. 16), i.e., to provide a method of dicing a wafer in a manner that
avoids defects such as cracking and chipping the semiconductor material and
burring along the cut edge of the metal layer (Reply Br. 6 (citing Mariani i-f 2)).
Appellants note Mariani achieves this result by forming trenches and filling them
with polymer through the entire section of material that will be cut to form
individualized semiconductor devices, so that the dicing saw will pass through
polymer and not the wafer material. Id. at 6-7. Appellants contend forming a
trench "ha[ ving]a bottom higher than a top surface of the third package
component" (claim 1) between Saito' s semiconductor chips 31 (first and second
package components) and filling the trench with a second polymer might prevent
cracking and chipping problems when separating the first and second package
components from each other. Id. at 7. Appellants argue, however, that since the
trench, as claimed, does not extend into the third package component, the problem
of cracking and chipping during the individualizing step would not be prevented
when sawing through Saito's interposer 30 (the third package component). Id. at
7.
We agree with Appellants that the Examiner has not identified adequate
support for finding that one of ordinary skill in the art would have been motivated
to modify Saito' s method to form a trench as recited in claim 1. Appellants have
argued persuasively that the Examiner's obviousness determination as to claim 1 is
not supported by a preponderance of the evidence, and is based on improper
hindsight reasoning. Accordingly, we do not sustain the rejection of claim 1 as
unpatentable over Saito in view of Mariani, or the rejections of its dependent
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Application 13/356,173
claims 2, 3, 5-7, 25, and 28 over the same combination, alone or in view of various
secondary references.
Claim 22
Claim 22 recites:
sawing the third portion of the first polymer to form a trench
between the first and the second package components;
... wherein [a] second polymer is filled into the trench to form
a polymer strip; and
performing a die-saw to saw the third package component into a
plurality of packages, . . . wherein the polymer strip is not sawed by
the die-saw.
The Examiner finds Saito describes the method recited in claim 22 with the
exception of the steps of sawing to form a trench and molding to form a polymer
strip. Final Act. 7-9. The Examiner relies on column 20, lines 22--42 of Saito for
a description of individualizing semiconductor devices in which a polymer strip
between first and second packages (104, 105) remains intact. Id. at 8-9. The
Examiner finds the ordinary artisan would have been motivated to modify Saito' s
method, based on Mariani' s teaching, to include steps of sawing to form a trench,
filling the trench with a second polymer, and molding to form a polymer strip. See
id. at 9-10.
Appellants argue Mariani forms trenches in the semiconductor wafer and
fills them with polymer for the purpose of preventing cracking and chipping when
the wafer is sawed. App. Br. 17-18. Appellants contend the ordinary artisan
would not have been motivated to form a trench and fill it with a second polymer
to form a polymer strip that remains intact (see id. at 18), noting the Examiner has
not identified evidence to support a finding that forming a polymer strip between
Saito's semiconductor chips 31 that remains intact, as recited in claim 22, would
prevent cracking and chipping problems during an individualizing step (see Reply
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Application 13/356,173
Br. 12-13). In the Response to Argument, the Examiner continues to assert that
the combination of Saito and Mariani discloses all of the claim 22 method steps.
See Ans. 7-8. The Examiner does not address, however, Appellants' arguments
that the ordinary artisan would not have had a reason to modify Saito to form a
trench and polymer strip as taught in Mariani.
Appellants have argued persuasively that the Examiner's obviousness
determination as to claim 22 is not supported by a preponderance of the evidence,
and is based on improper hindsight reasoning. Accordingly, we do not sustain the
rejection of claim 22 as unpatentable over Saito in view of Mariani, or the
rejections of its dependent claims 23, 24, and 27 over the same combination, alone
or in view of various secondary references.
Claim 8
Claim 8 recites:
dispensing an underfill to spaces between the first and the
second dies and the wafer, wherein the underfill comprises a portion
disposed in a gap bet\~1een the first and the second dies, and \~1herein
the underfill is not filled into a space between the second die and the
third die;
performing a curing step to cure the underfill;
after the curing step, sawing the portion of the underfill to form
a trench.
Rejection based on Saito and Mariani
As in the rejections of claims 1 and 22, the Examiner relies on Saito for a
teaching of dispensing an underfill 151 between the first and second dies and finds
Mariani provides motivation to modify Saito's method to form a trench in the
underfill between the first and second dies. See Final Act. 16-1 7; Ans. 9-10
(referencing Saito, Fig. 36). We agree with Appellants that the Examiner has not
explained adequately why one of ordinary skill in the art would have formed a
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Application 13/356,173
trench between Saito's components 104 and 105 based on the teachings of Mariani,
because these components are not separated by sawing. See App. Br. 20-21; supra
pp. 5-12 discussing the Examiner's rejections of claims 1 and 22; Saito, 19:43--47.
The Examiner relies on Patwardhan and Pogge for teachings of partially
curing the underfill material and performing a thermal step to anneal the underfill.
Final Act. 17. The Examiner has not identified teachings in these references that
cure the underlying deficiency with respect to the combination of Saito and
Mariani. Accordingly, we do not sustain the rejection of claims 8, 10-13, and 21
over Saito in view of Mariani, Patwardhan, and Pogge, or the rejection of claim 26
over these references, further in view of Chung.
Rejection based on Saito and Meyer
Meyer discloses a method of making "a semiconductor package configured
for use in a stacked package device." Meyer i-f 1. Meyer describes overmolding
semiconductor chips 10 with encapsulant 18, and using a saw to form a plurality of
recesses 18.1, 18.2, 18.3 in encapsulant 18 to expose contact elements 14, 15, 16 of
semiconductor chip 10. Id. i-fi-1 43--44. Meyer also discloses using a saw to form
through-hole 18.4 in encapsulant 18 between adjacent chips 10 and extending
through encapsulant 18 from the upper face to the lower face. Id. i-fi-1 43--44; Fig.
2C. Meyer describes applying layer 40 of a conductive material to the upper face
of encapsulate 18 to fill recesses 18.1, 18.2, 18.3 and form contact pads 50 located
outside the lateral contour line of chip 10 and connected to elements 14, 15, 16,
and applying layer 45 of the same conductive material to the lower face of the
package to form a contact pad and fill through-hole 18.4 to allow electrical
connection to contact element 16 via the lower face. Id. i-fi-145, 47--48; Fig. 2C.
The Examiner finds Saito discloses the claim 8 steps of bonding, dispensing
and curing, but does not specifically disclose sawing a portion of the underfill
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between chips 104, 105 to form a trench. Final Act. 21. The Examiner finds one
of ordinary skill in the art would have been motivated to modify Saito' s method by
forming a trench in the underfill as taught by Meyer in order to obtain a device of
reduced size and increase device functionality. Id. at 22.
Appellants argue Saito's first and second "package components 104 and 105
have already been flip-chip bonded to the underlying interposer 103" and the pads
of these components "are no longer available for forming [a] fan-out
package" as described in Meyer. Reply Br. 16. We are persuaded by Appellants'
argument that the Examiner has not identified support for finding that one of
ordinary skill in the art would have had a reason to modify Saito' s method.
The Examiner relies on Patwardhan and Pogge for teachings of partially
curing the underfill material and performing a thermal step to anneal the underfill.
Final Act. 22. The Examiner has not identified teachings in these references that
cure the underlying deficiency with respect to the combination of Saito and Meyer.
Accordingly, we do not sustain the rejection of claims 8 and 10-13 as unpatentable
over Saito in view of Meyer, Patwardhan, and Pogge.
In sum, Appellants have argued persuasively that the Examiner's
obviousness rejections are based on improper hindsight reasoning. Therefore, the
Examiner's decision to reject claims 1-3, 5-8, 10-13, and 21-28 is:
REVERSED
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