Ex Parte Lu et al

Patent Trial and Appeal Board

Jun 24, 2016

12846594 (P.T.A.B. Jun. 24, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/846,594 07/29/2010
43859 7590 06/28/2016
SLATER MATSIL, LLP
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252
FIRST NAMED INVENTOR
Lee-Chung Lu
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TSM09-0221 2276
EXAMINER
KIK, PHALLAKA
ART UNIT PAPER NUMBER
2851
NOTIFICATION DATE DELIVERY MODE
06/28/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@slatermatsil.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LEE-CHUNG LU, YI-KAN CHENG,
CHUNG-HSING WANG, CHEN-FU ALEX HUANG,
HSIAO-SHU CHAO, CHIN-YU CHIANG,
HO CHE YU, CHIH SHENG TSAI, and SHU YI YING
Appeal2015-001826
Application 12/846,5941
Technology Center 2800
Before JEFFREY T. SMITH, N. WHITNEY WILSON, and
DEBRA L. DENNETT, Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134 from the
Examiner's final rejection of claims 1---6 and 13-19.2 We have jurisdiction
pursuant to 35 U.S.C. § 6(b).
We REVERSE.
1 According to the Appeal Brief, the Real Party in Interest is Taiwan
Semiconductor Manufacturing Company, Ltd. (App. Br. 2.)
2 The Examiner indicates the subject matter of claims 7, 8, 10-12, and 20-24
is allowable. (Final Act. 7.)
Appeal2015-001826
Application 12/846,594
BACKGROUND
According to Appellants, the invention is directed to a method and
computer program product for the design of a semiconductor device
migrating to a smaller technology node. (Spec. i-f 2.) Claims 1 and 13 are
reproduced below from the Claims Appendix to the principal Brief:
1. A computer program product for providing an
adjusted electronic representation of an integrated circuit
layout, the computer program product having a non-transitory
computer readable medium with a computer program embodied
thereon, the computer program which when executed by a
processor provides the adjusted electronic representation of the
integrated circuit layout, the computer program comprising:
computer program code for generating full node cells
from a full node netlist;
computer program code for scaling the full node cells to
provide shrink node cells;
computer program code for generating a timing
performance of the full node cells and the shrink node cells;
computer program code for comparing the timing
performance of the full node cells to the timing performance of
the shrink node cells;
computer program code for generating derivative cells
from a respective shrink node cell, wherein each derivative cell
generated from the respective shrink node cell comprises a
variation of the respective shrink node cell, the variation
including at least one of an additional component in each
derivative cell that is not in the respective shrink node cell or a
feature of a component in each derivative cell that is a
modification of a corresponding component in the respective
shrink node cell;
computer program code for generating a timing
performance of the derivative cells;
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Appeal2015-001826
Application 12/846,594
computer program code for comparing the timing
performance of the derivative cells to the timing performance of
the full node cells; and
computer program code for generating a first netlist
comprising at least one of the shrink node cells, at least one of
the derivative cells, or a combination thereof.
13. A method for providing an adjusted electronic
representation of an integrated circuit layout, the method
compnsmg:
usmg one or more processor:
generating full node cells from a full node netlist;
scaling the full node cells to provide shrink node cells;
generating a timing performance of the full node cells
and the shrink node cells;
comparing the timing performance of the full node cells
to the timing performance of the shrink node cells;
generating derivative cells from a respective shrink node
cell; wherein each derivative cell generated from the respective
shrink node cell comprises a variation of the respective shrink
node cell;
generating a timing performance of the derivative cells;
comparing the timing performance of the derivative cells
to the timing performance of the full node cells; and
generating a first netlist comprising at least one
derivative cell that minimizes a difference between the timing
performance of the respective shrink node cell and a
corresponding full node cell.
The Examiner maintains, and Appellants appeal, the rejection of
claims 1---6 and 13-19 under 35 U.S.C. § 102(b) as anticipated by Regan (US
2003/0084418 Al; published May 1, 2003).
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Appeal2015-001826
Application 12/846,594
ANALYSIS3
The dispositive issue on appeal is: Did the Examiner err in
determining that Regan describes "generating derivative cells from a
respective shrink node cell, wherein each derivative cell generated from the
respective shrink node cell comprises a variation of the respective shrink
node cell," utilizing a computer program product having a computer
program code as recited in claim 1 or a method comprising using one or
more processor recited in claim 13? 4
We answer this question in the affirmative.
The complete statement of the rejection on appeal appears in the Final
Action. (Final Act. 2-7.)
The Examiner found Reagan teaches all of the elements of the claim,
including the providing full node cells from a full node netlist wherein the
design of an integrated circuit may be modified to use new cells in place of
old cells. (Final Act. 2-3 (citing Reagan i-fi-f 143-146, Fig. 24).)
We agree with the Appellants that the claimed invention is not
anticipated by the disclosure of Reagan.
Appellants argue Regan teaches migrating a circuit from one
manufacturing process to another wherein an old circuit having includes old
cells are replaced by new cells that have the same logical function as the old
cells. (App. Br. 9 (citing Regan i-fi-14---6, 53).) Appellants argue, contrary to
3 It is noted that the Examiner's Answer has four pages that are labeled as
"Page 3." We will address the Answer using the page numbers as they are
typically numbered, commencing with the mailing cover page as the first
page and the signature page as page 6. Appellants acknowledge this error in
the responsive brief. (Reply Br. 2.)
4 We limit our discussion to the independent claims 1 and 13.
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Application 12/846,594
the Examiner's position, Regan's paragraph 146 does not disclose
generating any cells from a scaled, new cell. (App. Br. 10.)
According to Regan:
The technique for modifying the circuit involves mapping a
library of new cells against the cells already in place for the old
circuit. The new cells will have the same logical function as the
old but may contain different topologies and combinations of
components to achieve these functions. The cell swapping
systems treats these cells as "black boxes" and is not concerned
with the detail of their construction beyond the outline of the
cell and the pins defining the input and output terminals for the
cell.
Regan i-f 53.
We agree with Appellants that Regan does not disclose generating
derivative cells from a respective scaled, new cell. Regan's system swaps a
new cell for another new cell, rather than generating a derivative cell from a
new cell. Consequently, Regan does not discloses generating derivative
cells from a respective shrink node cell, wherein each derivative cell
generated from the respective shrink node cell comprises a variation of the
respective shrink node cell, utilizing a computer program product having a
computer program code as recited in claim 1 or a method comprising using
one or more processor recited in claim 13.
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Appeal2015-001826
Application 12/846,594
DECISION
Under these circumstances, we cannot conclude that the Examiner has
met the minimum threshold of establishing anticipation under 35 U.S.C.
§ 102. Therefore, the rejection of claims 1---6 and 13-19 under§ 102(b) is
reversed.
REVERSED
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