Ex Parte Lu et al

Patent Trial and Appeal Board

Nov 14, 2014

12502211 (P.T.A.B. Nov. 14, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/502,211 07/13/2009 Yong Lu 1011.14894.00 5779
75742 7590 11/14/2014
MUETING, RAASCH & GEBHARDT, P.A.
P.O. Box 581336
Minneapolis, MN 55458-1336
EXAMINER
ALROBAIE, KHAMDAN N
ART UNIT PAPER NUMBER
2824
MAIL DATE DELIVERY MODE
11/14/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_________________

Ex parte YONG LU, HONGYUE LIU, MAROUN KHOURY,
and YIRAN CHEN
_________________

Appeal 2012-011979
Application 12/502,211
Technology Center 2800
_________________

Before RICHARD E. SCHAFER, DEBORAH KATZ, and
JON M. JURGOVAN Administrative Patent Judges.

KATZ, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2012-011979
Application 12/502,211

2
Appellants1 seek our review, under 35 U.S.C. § 134(a), of the
Examiner’s decision to reject claims 1-20. (Notice of Appeal.) We have
jurisdiction under 35 U.S.C. § 6(b). We AFFIRM.
Appellants’ Specification is directed to resistive sense memory
apparatuses. Resistive sense memory cells rely on the direction of
magnetization to form either low or high resistance, which provides for
either a “0” or “1” signal. (Specification (“Spec.”), ¶¶ 22-23.) According to
Appellants’ Specification, this type of memory requires a large current for
writing. While MOSFET select transistors can be used to provide a large
current, they also require a large area. (Id., ¶ 4.) Appellants provide a
device with reduced area requirements. Specifically, Appellants provide a
resistive sense memory apparatus with a bipolar select transistor that has a
high drive current for its size and that shares one contact across multiple
memory cells. (Spec. ¶ 5.)
Appellants’ independent claims 1 and 11 are directed to a resistive
sense memory apparatus having a plurality of transistors with a particular
arrangement of contacts. (Appeal Brief (“App. Br.”) 9 and 10-11.)
Appellants’ claim 19 is directed to a method of using such an apparatus. (Id.
at 12.)
The Examiner rejected claims 1, 2, 4-9, 12-17 under 35 U.S.C.
§ 103(a) over Forbes2 in view of Chen.3 (Office Action dated November 1,
2011 (“O.A.”) at 2-5.)

1 The real party in interest is said to be Seagate Technology, LLC. (App. Br.
2.)
2 US Patent Application Publication 2001/0046154 A1, published November
29, 2001.
Appeal 2012-011979
Application 12/502,211

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Appellants argue against the combination of Forbes and Chen without
providing separate arguments for any of the rejected claims. We review the
rejection of claim 1 as representative. See 37 C.F.R. § 41.37(c)(1)(iv).
Appellants’ claim 1 recites:
A resistive sense memory apparatus comprising:
a bipolar select device comprising:
a semiconductor substrate;
a plurality of transistors disposed in the semiconductor
substrate and forming a row or [sic] transistors, each transistor
comprising an emitter contact and a collector contact, wherein each
collector contact is electrically isolated from each other and each
emitter contact is electrically isolated from each other, a gate contact
extends along a channel region between the emitter contact and a
collector contact;
a base contact is disposed within the semiconductor substrate
such that the emitter contact and a collector contact is between the
gate contact and the base contact; and
a plurality of resistive sense memory cells, wherein one of the
plurality of resistive sense memory cells is electrically between one of
the collector contacts or emitter contacts and a bit line.

(App. Br. 9, Claims App’x.)
The Examiner finds that Forbes teaches a bipolar select device having
a semiconductor substrate, a plurality of transistors as claimed, and a base
contact as claimed. (O.A. 3, citing Forbes at Figs. 2, 3A, and 3B.) Though
Forbes does not expressly teach resistive sense memory cells, the Examiner
holds that an apparatus comprising a bipolar selective device with such
memory cells would have been obvious to skilled artisans for two reasons.
First, the Examiner cites the teaching in Forbes that the device is applicable

3 US Patent Application Publication 2007/0297223 A1, published December
27, 2007.
Appeal 2012-011979
Application 12/502,211

4
to any type of memory circuit. (Id., citing Forbes, ¶ 28.) Though Forbes
lists several types of memory circuits, it does not expressly include resistive
sense memory.
Second, the Examiner combines the teachings of Forbes and Chen.
(O.A. 4.) Chen teaches a memory device with a plurality of resistive sense
memory cells. (Chen, abstract.) The Examiner finds that those of skill in
the art would have had reason to use the transistors of Forbes in the Chen
device because the bipolar-MOSFET transistors of Forbes conduct a higher
current and thus would increase the memory speed in Chen. (O.A. 4, citing
Forbes ¶ 26: “Thus, the access device provides the advantage of increased
speed in reading the data stored in the memory cell by allowing the capacitor
to be discharged more quickly.”)
Appellants argue that the Examiner erred in combining Forbes and
Chen because, according to Appellants, including the transistors of Forbes in
the device of Chen would destroy the function of the Chen device. (App. Br.
4-7.) Appellants point to paragraph 26 of Forbes, which discusses a
“vertical access device” having a bipolar-MOSFET transistor shown in
Figure 3A. Paragraph 26 explains that the bipolar junction transistor of the
vertical access device conducts a higher current than the counterpart field
effect (MOSFET) transistor. This allows the access device to read data
stored in the memory cell faster because the capacitor discharges more
quickly. (Forbes, ¶ 26.) According to Appellants, this feature is in contrast
to the STT-RAM memory of Chen, which has read current densities of the
read operations that are less than the current densities of the write
operations. (App. Br. 6, citing Chen at ¶ 14 and Fig. 5.) Appellants assert
that the higher read current density of Forbes would disturb the data written
Appeal 2012-011979
Application 12/502,211

5
on the memory device of Chen. Appellants also assert that the objective of
Chen to improve read and write margins is contrary to the device of Forbes,
which produces a lower read and write margin. (App. Br. 6-7.)
We are not persuaded by Appellants’ arguments. The parameters of
increasing or decreasing the currents in Forbes and Chen to which
Appellants point are relative terms. Appellants have not directed us to
evidence that the actual “higher” read current density of Forbes is too high
for the data written on the memory device of Chen. Without evidence that
an increase is too high, we are not persuaded that there would be no
advantage to any increased speed when reading data stored in a capacitor, as
the Examiner found.
Furthermore, as the Examiner explains, Chen improves the read and
write margin by calculating and comparing the ratios of maximum and
minimum low resistance states of the read and write currents and
configuring the memory accordingly, not by simply lowering the read
current density. (Answer 3-4, citing Chen, abstract.) Accordingly, we are
not persuaded that merely because the device of Forbes increases the read
density, it would be contrary to the objective of Chen.
Appellants have not persuaded us that the examiner erred in holding
that their claimed apparatus would have been obvious over at least the
combination of Forbes and Chen.
The Examiner also rejected claims 19 and 20 under 35 U.S.C.
§ 103(a) over Chen in view of Forbes (O.A. 11-15) and claims 3, 10, and 18
under 35 U.S.C. § 103(a) over Forbes and Chen and further in view of
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Application 12/502,211

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Okhonin4 (Id. 15-16). Appellants do not provide separate arguments against
these rejections. We are not persuaded that the rejections were made in error
for the reasons provided above.

Conclusion
Upon consideration of the record and for the reasons given, the
rejection of claims 1-20 are sustained.
We affirm the decision of the Examiner.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136.

AFFIRMED

tc

4 Okhonin, US Patent Application Publication 2008/0025083 A1, published
January 31, 2008.