Ex Parte Lowrey

Board of Patent Appeals and Interferences

Oct 19, 2009

10939275 (B.P.A.I. Oct. 19, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte TYLER A. LOWREY
____________

Appeal 2009-002153
Application 10/939,275
Technology Center 2100
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Decided: October 20, 2009
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Before LEE E. BARRETT, JOHN A. JEFFERY, and THU A. DANG,
Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1-34. Claims 35-44 are canceled. See Amendment
received January 19, 2007. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

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STATEMENT OF THE CASE
Appellant invented a system that saves data when power is lost with
less power consumption. The system 500 includes controller 510, phase
change memory 530, buses 514 and 522, and volatile memory 570. The
controller 510 may directly communicate with the phase change memory
530 without any intervening buffer through a bus 514.1
Claim 1 is illustrative:
1. A method comprising:

forming a processor-based system including a central
processing unit and a phase change memory directly accessible
by said unit.

The Examiner relies on the following prior art references to show
unpatentability:
Jones US 2002/0156983 A1 Oct. 24, 2002

Ogiwara US 7,053,431 B2 May 30, 2006
(filed Feb. 13, 2004)
Webopedia, www.webopedia.com/TERM/M/microprocessor.html (last
visited Nov. 28, 2007)

The Examiner’s rejection is as follows:
Claims 1-34 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Jones and Ogiwara. Ans. 3-8.

1 See generally Spec. 5-6; Figs. 1-2.
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Rather than repeat the arguments of Appellant or the Examiner, we
refer to the Briefs and the Answer2 for their respective details. In this
decision, we have considered only those arguments actually made by
Appellant. Arguments, which Appellant could have made but did not make
in the Briefs, have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii).
We group the claims as follows: (1) claims 1, 2, 4-10, and 20-30; (2)
claims 3 and 24; (3) claims 11-19; and (4) claims 31-34. Each grouping will
be addressed separately.

Claims 1, 2, 4-10, and 20-30
Regarding representative claim 1,3 the Examiner finds Jones discloses
the recited method except for a phase change memory. Ans. 3. The
Examiner relies on Ogiwara to teach substituting the non-volatile memory of
Jones for a phase change memory to allow data to be written more quickly
and more often. Ans. 4. Appellant argues that the hard disk microprocessor
310 disclosed in Jones is not a central processing unit as recited in claim 1.
App. Br. 10; Reply Br. 1-2.

ISSUE
The following issue has been raised in this appeal:

2 Throughout this opinion, we refer to: (1) the Appeal Brief filed August 2,
2007 and supplemented September 24, 2007; (2) the Examiner’s Answer
mailed January 2, 2008; and (3) the Reply Brief filed February 20, 2008.
3 Appellant argues claim 1. App. Br. 10. Claims 2, 4-10, and 20-30 are not
separately argued. See App. Br. 10-11. Accordingly, we select claim 1 as
representative. See 37 C.F.R. § 41.37(c)(1)(vii).
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Has Appellant shown that the Examiner erred in rejecting claim 1
under 35 U.S.C. § 103 by finding that Jones teaches a processor-based
system having a phase change memory directly accessible by the central
processing unit?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
Appellant’s Disclosure
(1) The Specification does not use the phrase, “central processing
unit.” See generally Specification.
(2) The Specification describes a controller 510. The controller can be
one or more microprocessors, digital signal processors, or microcontrollers.
Spec. 4:3-5 and 5:7; Fig. 1.
(3) Appellant admits Jones discloses a central processing unit (CPU).
See App. Br. 10.

Jones
(4) Jones discloses a data processing system 200 having buses (e.g.,
206), adapters 212, 210, 218, and 219, and hard disk 226. The hard disk
drive 300 has a hard disk microprocessor 310 connected to various
components as shown by horizontal arrows, including power detection unit
312, cache 316, and nonvolatile memory 330. ¶¶ [0018]-[0023]; Figs. 2-3.
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(5) Jones discloses the nonvolatile memory 330 or 430 includes flash
random access memory (RAM) or flash memory. ¶¶ [0023] and [0027];
Figs. 3-4.
(6) Jones discloses the microprocessor 310 may receive data from a
CPU through drive interface 318. ¶ [0022].

Ogiwara
(7) Ogiwara teaches that phase change memory is new type of
nonvolatile memory that allows data to be written more quickly and
rewritten more times than existing flash memories. Col. 1, ll. 16-30.

PRINCIPLES OF LAW
During examination of a patent application, a claim is given its
broadest reasonable construction “in light of the specification as it would be
interpreted by one of ordinary skill in the art.” In re Am. Acad. of Sci. Tech
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (internal citations and quotations
omitted). “[W]hen interpreting a claim, words of the claim are generally
given their ordinarily and accustomed meaning, unless it appears from the
specification or file history that they were used differently by the inventor.”
In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
“‘Functional’ terminology may render a claim quite broad. By its
own literal terms a claim employing such language covers any and all
embodiments which perform the recited function.” In re Swinehart, 439
F.2d 210, 213 (CCPA 1971).

ANALYSIS
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The main dispute in this appeal is whether Jones discloses “a central
processing unit” as recited in representative claim 1. Upon reviewing the
Specification, there is no definition or discussion of a “central processing
unit.” See FF 1. Rather, the disclosure addresses a controller 510 that can
be one or more microprocessors (FF 2). Thus, regardless of how a “central
processing unit” is defined (see App. Br. 10; Ans. 9), the Specification uses
the term “controller” differently than Appellant’s definition and indicates the
term “central processing unit” is another phrase for a controller – an
interpretation that comports with the “Summary of the Claimed Subject
Matter” section of Appellant’s Brief. See App. Br. 7 (indicating that
controller 510 in Figure 1 of the present application corresponds to the
recited “central processing unit”); see also Paulsen, 30 F.3d at 1480. When
considering the phrase “central processing unit” in light of the Specification
and as interpreted by an ordinarily skilled artisan, we find the broadest
reasonable construction includes one or more microprocessors. 4
Jones discloses such a “central processing unit” or microprocessor
310. FF 4. This microprocessor is also central to many other components,
including a cache or volatile memory 316 and nonvolatile memory 330. See
id. We therefore find that, contrary to Appellant’s assertions (App. Br. 10-
11), Jones discloses a central processing unit as recited in claim 1. The
nonvolatile memory 330 is directly accessible by, and directly coupled to,
the unit 310 as shown by the horizontal arrow. See FF 4. Moreover, as
explained and as not challenged by the Appellant (see generally Appeal
Brief), Ogiwara amply teaches replacing the nonvolatile memory 330 with a

4 We note in passing that independent claim 20 recites “said controller”
along with “a central processing unit” in line 4.
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phase change memory so as to allow data to be written more quickly and
rewritten more times than existing flash memories. See Ans. 4; see also FF
7.
Additionally, the phrase, “directly accessible by said unit,” in claim 1
is a functional limitation that only requires the phase change memory to be
inherently capable of being directly accessible to the CPU and does not
require a direct coupling of the phase change memory to the CPU. See
Swinehart, 439 F.2d at 213. Therefore, even assuming, without deciding,
that the microprocessor 310 could somehow not be considered a CPU, Jones
and Ogiwara still collectively teach a CPU (see FF 3 and 6) and a phase
change memory directly accessible by said unit (FF 7). That is, Appellant
has admitted that Jones discloses a CPU (FF 3), and the nonvolatile memory
330 is inherently capable of being directly accessible to the CPU through a
bus or other communication interface.
For the above reasons, Appellant has not shown error in the
obviousness rejection of claim 1 based on the collective teachings of Jones
and Ogiwara. Accordingly, we sustain the rejection of claim 1 and claims 2,
4-10, and 20-30 which fall with claim 1.

Claims 3 and 24
Representative claim 35 recites the volatile memory is coupled
directly to the central processing unit and directly to the phase change
memory. The Examiner finds that Jones discloses this feature. Ans. 4.

5 Appellant argues claims 3 and 24 as a group. App. Br. 10-11.
Accordingly, we select claim 3 as representative. See 37 C.F.R. §
41.37(c)(1)(vii).
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Appellant argues that Jones does not disclose or teach the volatile memory is
directly coupled to the non-volatile memory 330 (App. Br. 11; Reply Br. 2-
3) and that there is no teaching of a CPU coupled directly to a phase change
memory (Reply Br. 2).

ISSUE
The following additional issue has been raised in this appeal:
Has Appellant shown that the Examiner erred in rejecting claim 3
under § 103 by finding that Jones and Ogiwara collectively teach or suggest
coupling the volatile memory directly to the phase change memory?

ADDITIONAL FINDINGS OF FACT
The record supports the following additional findings of fact (FF) by a
preponderance of the evidence.
Jones
(8) Jones discloses a hard drive 300 with cache 316 and nonvolatile
memory 330 connected to the hard disk microprocessor 310. Jones discloses
a hard disk controller 400 with the cache 416 and nonvolatile memory 430
connected to the microprocessor 410. Figs. 3-4.
(9) Jones discloses a nonvolatile random access memory attached to
the write back cache. ¶ [0007].

ANALYSIS
The limitations of claim 3 differ significantly from claim 1. In
particular, claim 3 recites a structural relationship of coupling the volatile
memory directly to (1) the CPU and (2) the phase change memory. Jones
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does not disclose or teach this direct structural coupling of the volatile
memory 316 or 416 to the CPU or non-volatile memory in Figures 3 and 4.
See FF 8. Also, while Jones states the non-volatile memory is “attached” to
the cache, there is no discussion that the attachment or coupling is direct
such the disclosure meets the limitation “coupling said volatile memory . . .
directly to said phase change memory” in claim 3. See FF 9. Furthermore,
Ogiwara fails to cure this deficiency.
For the above reasons, we find error in the Examiner’s rejection of
claim 3 and claim 24 which recites commensurate limitations.

Claims 11-19
Representative claim 116 recites a phase change memory. The
remainder of the claim is a functional limitation that the memory is directly
accessible by a CPU and, thus, only requires that the memory is inherently
capable of being directly accessible by the CPU. See Swinehart, 439 F.2d at
213. Thus, for the same reasons discussed above in connection with claim 1,
we find no error in the Examiner’s rejection of claim 11 and claims 12-19
which fall with claim 11.

Claims 31-34
Representative claim 317 recites a method that includes a phase
change memory coupled directly to a central processing unit. The Examiner

6 Appellant does not separately argue claims 11-19. App. Br. 10-11.
Accordingly, we select claim 11 as representative. See 37 C.F.R.
§ 41.37(c)(1)(vii).
7 Appellant argues claims 31-34. App. Br. 11. Accordingly, we select claim
34 as representative. See 37 C.F.R. § 41.37(c)(1)(vii).
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find Jones and Ogiwara collectively teach this step. Ans. 7-8. Appellant
argues that the cited references do not suggest a phase change memory
directly coupled to a central processing unit to store certain coding. App.
Br. 11; Reply Br. 2-4.

ISSUE
The following additional issue has been raised in this appeal:
Has Appellant shown that the Examiner erred in rejecting claim 31
under § 103 by finding that Jones and Ogiwara collectively teach or suggest
the step of “storing code on a phrase change memory coupled directly a
central processing unit?”

ADDITIONAL FINDINGS OF FACT
The record supports the following additional findings of fact (FF) by a
preponderance of the evidence.
Jones
(10) Jones states that the operating system (e.g., programming and
applications) can be located on storage devices, such as hard disk drive 226,
and loaded into the main memory 204. The processes of the invention can
be stored on a computer readable media, having coded formats, and then
incorporated into the storage device by installing firmware and updating
flash memory within the devices. ¶¶ [0016] and [0032].

ANALYSIS
As explained above, we find that Jones discloses a microprocessor or
central processing unit 310. This central processing unit 310 is directly
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coupled to non-volatile memory 330. See FF 4. Jones teaches the non-
volatile memory can be flash memory (FF 5), but does not teach that the
non-volatile memory 330 is a phase change memory. See Ans. 7. Ogiwara
teaches a new type of non-volatile or flash memory called a phase change
memory. FF 7. A phase change memory allows data to be written more
quickly and more times than do existing flash memories. See id. Thus,
combining Ogiwara with Jones would have predictably resulted in a
substitution of Jones’ flash memory for Ogiwara’s phase change memory,
resulting in an improved system that writes data more quickly and permits
rewriting more times than Jones’ flash memory. See KSR Int’l Co. v.
Teleflex, Inc., 550 U.S. 398, 416-17 (2007). Moreover, this resulting system
would directly couple the central processing unit 310 with the substituting
memory.
Jones further teaches that the operating system, firmware, or code can
be installed in the memory of storage devices to perform the invention’s
processes. FF 10. Using the background knowledge of an ordinarily skilled
artisan, one skilled in the art would have recognized installing the firmware
or coding within nonvolatile memory (e.g., 330) of the storage device (e.g.,
drive 300) so that the coding is more permanent. See KSR, 550 U.S. at 418.
Thus, in view of Ogiwara’s phase change memory, Jones and Ogiwara
collectively teach storing code on a phase change memory that is coupled
directly to a central processing unit.
For the above reasons, we find no error in the Examiner’s rejection of
claim 31 and claims 32-34 which fall with claim 31.

CONCLUSIONS
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(1) Appellant has not shown that the Examiner erred in rejecting: (a)
claims 1, 2, and 4-19 under § 103 by finding that Jones teaches a system
having a phase change memory directly accessible by the central processing
unit and (b) claims 20-30 under § 103 by finding that Jones teaches a system
having a phase change memory directly coupled to the central processing
unit.
(2) Appellant has shown that the Examiner erred in rejecting claims 3
and 24 under § 103 by finding that Jones and Ogiwara collectively teach
coupling the volatile memory directly to the phase change memory.
(3) Appellant has not shown that the Examiner erred in rejecting
claims 31-34 under § 103 by finding that Jones and Ogiwara collectively
teach or suggest the step of “storing code on a phrase change memory
coupled directly a central processing unit.”

DECISION
We have sustained the Examiner’s rejection with respect to claims 1,
2, 4-23, and 25-34 on appeal and have not sustained the Examiner’s
rejection of claims 3 and 24. Therefore, the decision of the Examiner to
reject claims 1-34 is affirmed-in-part.
No period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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