Ex Parte Lovett

Patent Trial and Appeal Board

Aug 4, 2016

13308333 (P.T.A.B. Aug. 4, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/308,333 11130/2011
15747 7590 08/08/2016
Dorsey & Whitney LLP-IP Dept.-MTI
Columbia Center
701 5th Avenue, suite 6100
Seattle, WA 98104-7043
FIRST NAMED INVENTOR
Simon J. Lovett
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
501254.12
(P030269.US.06)
EXAMINER
LI,ZHUOH
5548
ART UNIT PAPER NUMBER
2133
NOTIFICATION DATE DELIVERY MODE
08/08/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ip.docket.se@dorsey.com
bingemang@dorsey.foundationip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SIMON J. LOVETT
Appeal2015-001930
Application 13/308,333
Technology Center 2100
Before THU A. DANG, JOHNNY A. KUMAR, and
LARRY J. HUME, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 2-5, 7-10, and 19-22.2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 According to Appellant, the real party in interest is Micron Technology,
Inc. App. Br. 3.
2 Claims 1, 6, and 11-18 have been cancelled.
Appeal2015-001930
Application 13/308,333
STATEMENT OF CASE
Invention
The disclosed and claimed invention on appeal is directed to a
memory device having a DRAM memory core with asynchronous
functionality and circuitry to automatically detect whether an asynchronous
or synchronous memory access operation is requested. Spec. 4.
Representative Claim
2. A mode detection circuitry comprising:
asynchronous detection circuitry configured to receive a
plurality of control signals, and responsive to a particular
combination of the control signals, generate an asynchronous
mode control signal; and
[L 1] a delay circuit configured to receive the
asynchronous mode control signal [L2] and delay the
asynchronous mode control signal a delay amount based, at
least in part, on a cycle time of a memory array including a
plurality of memory cells, wherein a memory operation of the
memory array occurs during the cycle time, [L3] the delay
circuit further configured to prevent an output signal from
being generated in response to receiving a transition of the
asynchronous mode control signal before the delay amount
elapses.
App. Br. 15 (emphasis added).
Rejections on Appeal
The Examiner rejected claims 2-5, 7, 9, 10, and 19 on the ground of
nonstatutory obviousness-type double patenting (OTDP) as being
unpatentable over claims 1--41 of U.S. Patent No. 6,920,524, claims 1-18 of
2
Appeal2015-001930
Application I3/308,333
U.S. Patent No. 7,320,049, claims I-2I of U.S. Patent No. 7,506, I26, and
claims I-I9 of U.S. Patent No. 7,640,4I3 (Final Act. 2--4). 3
The Examiner rejected claims 2-5, 7, 9, IO, and I9-22 under
35 U.S.C. § I03(a) as being unpatentable over Gray (US 6,658,544 B2, Dec.
2, 2003) in view of Shiomi (US 5, I24,589, June 23, I 992) (Final Act. 4--7).
The Examiner further rejected claim 8 adding Haess (US 5,524,270,
June 4, I 996) (Final Act. 7).
Contentions
I. Regarding the § I 03 rejection of claim 2, Appellant contests
limitations LI, L2 and L3. App. Br. 7-I2; Reply Br. 2-5. Appellant
particularly contends with respect to LI, inter alia:
The asynchronous memory control signal generator circuit 80
generates the asynchronous memory control signal (AS). The
asynchronous memory control signal generator circuit 80 does
not receive the asynchronous memory control signal (AS), nor
does the asynchronous memory control signal generator circuit
80 delay the asynchronous memory control signal (AS).
3 While acknowledging this OTDP rejection (App. Br. 3), Appellant does
not contest this rejection in the Appeal Brief. However, there appears to be
some ambiguity with respect to whether this rejection is before us on appeal.
"The non-statutory obviousness-type double patenting rejection of claims 2-
7, 9, I 0 and I 9 will be withdrawn until a proper terminal disclaimer is filed
and approved." Advisory Action mailed May 2, 20I4 (emphasis added); Cf
"Every ground of rejection set forth in the Office action dated 1/I 7 /20 I 4
from which the appeal is taken is being maintained by the examiner except
for the grounds of rejection (if any) listed under the subheading
'WITHDRAWN REJECTIONS."' Ans. 2. We note the Examiner's Answer
does not contain a "WITHDRAWN REJECTIONS" section. For purposes
of our Decision, we assume the Examiner's statement in the Advisory
Action is a typographical error such that the OTDP rejection is before us on
appeal.
3
Appeal2015-001930
Application 13/308,333
The Examiner cites Gray at col. 4, line 33-col. 5, line 24
as disclosing the delay of an asynchronous control signal on
page 4 of the Final Office Action (FOA). However, in this
section, Gray describes delaying the address signals
(A[ n ]/An TD), not the asynchronous memory control signal
(AS) on signal pathway 26.
App. Br. 9-10.
At most, Gray teaches the HOOK signal is delayed, which is a
control signal generated by the synchronous memory 30.
Reply Br. 3.
II. Appellant further contends with respect to L2, inter alia:
Shiomi fails to teach a delay circuit as recited in the
combination of limitations of claim 2 ....
App. Br. 10.
Shiomi teaches signals are delayed in synchronous mode, but
signals are not delayed in asynchronous mode, contrary to the
assertion of the Examiner.
App. Br. 11-12.
[T]he STRAM of Shiomi does not delay an asynchronous mode
control signal a delay amount based, at least in part, on a cycle
time of a memory array.
Reply Br. 4 (italics omitted).
III. Appellant further contends with respect to L3, inter alia:
Shiomi describes delaying the synchronous controls signals,
and not delaying the asynchronous control signals. Because the
asynchronous control signals are delivered without delay, the
teaching of delays in memory control signals when the memory
is in synchronous mode cannot correspond to "the delay circuit
further configured to prevent an output signal from being
generated in response to receiving a transition of the
asynchronous mode control signal .... "
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Appeal2015-001930
Application 13/308,333
App. Br. 12.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments that the Examiner erred. App. Br. 8-13; Reply Brief 2-5.
Further, we have reviewed the Examiner's response to claim 2 that has been
argued by Appellant. Ans. 2-7. With regard to claims 2-5, 7-10,
and 19-22, we adopt as our own (1) the findings and reasons set forth by the
Examiner in the action from which this appeal is taken and (2) the reasons
set forth by the Examiner in the Examiner's Answer in response to
Appellant's Appeal Brief. We concur with the conclusions reached by the
Examiner. We highlight and address specific findings and arguments for
emphasis as follows.
Rejection of Claims 2-5, 7-10, and 19-22 under 35 U.S.C. § 103
Based on Appellant's arguments, we decide the appeal of claims 2-5,
7-10, and 19-22 on the basis of representative claim 2. See 37 C.F.R.
§ 41.37(c)(l)(iv). Appellant has not argued any of the other claims in this
group with particularity. 37 C.F.R. § 41.37(c)(l)(iv).
Issue 1: Under § 103, did the Examiner err by finding that Gray and
Shiomi collectively would have taught or suggested "[L 1] a delay circuit
configured to receive the asynchronous mode control signal and delay the
asynchronous mode control signal," within the meaning of representative
claim 2 (emphasis added)?
The Examiner finds, and we agree, Gray teaches and suggests "a
delay circuit [is] configured to receive the asynchronous mode control signal
and delay the asynchronous mode control signal a delay amount" (Ans. 3
(citing Gray col. 4, 11. 33--49 and Figs. 2--4)). We note the cited portion of
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Appeal2015-001930
Application 13/308,333
Gray teaches and suggests the delay of input signals A[O]-A[n] by a time
delay TD 1 to produce signals AOTD-AnTD. Further, the Examiner cites a
delay of an output signal, AS, indicated by the Examiner as corresponding to
the asynchronous mode signal, by a HOOKP signal, until a time delay TD3
ends (Ans. 3 (citing Gray col. 5, 1. 25---col. 6, 1. 7)). The Examiner
essentially points out that if signals are delayed upstream of the component
labeled "asynchronous memory control signal generator circuit 80" shown at
the output of Figure 2, then, the corresponding output AS will be delayed
downstream (Ans. 3).
Although Appellant argues that the asynchronous memory control
signal generator circuit 80 of Gray's Figure 2 does not receive or delay the
asynchronous memory control signal, the Examiner finds the address control
signals and the HOOK signal to contain the delays instead of circuit 80. In
addition, Appellant has not particularly defined the term "asynchronous
mode control signal" in the claim other than that is generated, received and
delayed. See also In re Self, 671F.2d1344, 1348 (CCPA 1982)
("[A]ppellant's arguments fail from the outset because ... they are not based
on limitations appearing in the claims."). See Superguide Corp. v. DirecTV
Enter., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004) (particular embodiments
appearing in the written description must not be read into the claim if the
claim language is broader than the embodiment).
Here, the Examiner finds, with which we agree, Gray teaches or
suggests address signals (Ans. 3), to be received and delayed by the circuit
of Figure 2 before being transformed at the output into the final
asynchronous mode control "AS" signal. For these reasons, we are
unpersuaded the Examiner erred in finding that Gray teaches or suggest an
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Application 13/308,333
"asynchronous mode control signal" (Final Act. 4) and delay circuit, as
claimed. Thus, we find no deficiencies regarding the Examiner's reliance on
Gray in the rejection of L 1.
Issue 2: Under § 103, did the Examiner err by finding that Gray and
Shiomi collectively would have taught or suggested "[L2] and delay the
asynchronous mode control signal a delay amount based, at least in part, on
a cycle time of a memory array," within the meaning of representative
claim 2 (emphasis added)?
The Examiner primarily relied on Gray to teach delaying the
asynchronous mode control signal a delay amount based, at least in part, on
a cycle time of a memory array (Final Act. 4 (citing Gray col. 4, 1. 33---col. 5,
1. 24)), using the combination with Shiomi to lend additional support to the
relation of a delay to a memory array (Final Act. 5). The Examiner cites
Gray as preventing a HOOKP signal being generated before a time delay
TD3 (Ans. 3 (citing Gray col. 5, 1. 25---col. 6, 1. 7)). We note that the cited
passage specifically states that the HOOK signal indicates when a memory
access has been completed and this will result in delaying the output of the
asynchronous mode control AS signal downstream. Shiomi further serves to
buttress the Examiner's finding by providing additional evidence of a delay
in a memory cell access in order to complete a synchronous mode operation
before an asynchronous mode operation (Final Act. 5).
Thus, we find no deficiencies regarding the Examiner's interpretation
of Gray and Shiomi in the rejection of L2.
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Application 13/308,333
Issue 3: Under§ 103, did the Examiner err by finding that Gray and
Shiomi collectively would have taught or suggested "[L3] the delay circuit
further configured to prevent an output signal from being generated in
response to receiving a transition of the asynchronous mode control signal
before the delay amount elapses," within the meaning of representative
claim 2 (emphasis added)?
At the outset, it is noted that the Examiner relied on Gray and not
Shiomi to teach limitation L3 (Final Act. 5; Ans. 6). Following the
discussion of contentions I and II, supra, Gray teaches asynchronous mode
control signals that are delivered with delay caused by the HOOKP signal.
The Examiner finds that the HOOKP signal prevents the output signal AS
from being generated in response to the HOOKP signal before a time delay
TD3 elapses (Ans. 6). However, Appellant contends that the HOOKP signal
is synchronous and not asynchronous and, therefore, cannot represent a
transition of an asynchronous mode control signal. Appellant's specification
states:
However, in the event a PULSE_SYNC pulse is generated by
the synchronous mode detection circuitry 120 prior to the time
delay td elapsing, the refresh timer 130 will be reset and
deactivated to prevent a PULSE_OUT pulse from being
generated by the refresh timer 130.
Spec. i-f 20 (emphasis added).
In other words, a transition of an asynchronous mode control signal
occurs when a synchronous control signal such as PULSE-SYNC
corresponding to HOOKP is generated. Therefore, we find no deficiencies
in the Examiner's rejection of L3.
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Application 13/308,333
We accordingly sustain the Examiner's rejection of claim 2 and
claims 3-5, 7-10, and 19-22 which were grouped together with claim 2.
CONCLUSION
The Examiner did not err in rejecting 1) claims 2-5, 7, 9-10,
and 19-22 under 35 U.S.C. § 103(a) as being unpatentable over the
combination of Gray and Shiomi; 2) claim 8 as being unpatentable over the
combination of Gray, Shiomi, and Haess; and 3) claims 2-5, 7, 9, 10, and 19
on the ground of nonstatutory obviousness-type double patenting.
DECISION
The Examiner's rejections of claims 2-5, 7-10, and 19-22 are
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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