Ex Parte LOH et al

Patent Trial and Appeal Board

Aug 2, 2016

13328393 (P.T.A.B. Aug. 2, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/328,393 12/16/2011 Gabriel H. LOH
45114 7590 08/04/2016
HARRITY & HARRITY, LLP
11350 Random Hills Road
SUITE 600
FAIRFAX, VA 22030
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
110186 3898
EXAMINER
RIZK, SAMIR W ADIE
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
08/04/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docket@harrityllp.com
mpick@harrity llp .com
ptomail @harrity llp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GABRIEL H. LOH, JAMES M. O'CONNOR,
MICHAEL IGNATOWSKI, NUWAN S. JA YASENA,
and BRADFORD M. BECKMANN
Appeal2015-001932
Application 13/328,393
Technology Center 2100
Before JOHNNY A. KUMAR, LINZY T. McCARTNEY, and
JAMES W. DEJMEK, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2015-001932
Application 13/328,393
Appellants 1 appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1, 3-8, 10-14, and 16-23.2 We have jurisdiction under 35 U.S.C.
§ 6(b ).
We affirm.
STATEMENT OF CASE
Invention
The claimed invention on appeal is directed to a separate logic chip
integrated with one or more memory chips on a single die. Spec. 3--4.
Exemplary claims 1, 4, and 5 under appeal read as follows:
1. A method comprising:
receiving, by a logic chip of a memory architecture, a
request to modify values of data in at least one memory chip of
a plurality of memory chips of the memory architecture,
the plurality of memory chips and the logic chip being on
a single die of the memory architecture,
the plurality of memory chips being included in a stack
of memory chips on the single die,
the request being received from a processor that is not on
the single die;
transferring, by the logic chip and based on the request,
the values of data from the at least one memory chip to the
logic chip;
modifying, via the logic chip and based on the request,
the values of data to obtain modified values of data; and
1 According to Appellants, the real party in interest is Advanced Micro
Devices, Inc. App. Br. 3.
2 Claims 2, 9, and 15 have been canceled. Final Act. 2.
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writing, from the logic chip and to the at least one of
memory chip, the modified values of data.
4. The method of claim 3, where the request includes
an atomic increment command, and
where:
transferring the values of data includes transferring the
values of data from a specified address associated with the at
least one memory chip,
modifying the values of data includes modifying the
values of data by incrementing the values of data by an
increment amount specified by the atomic increment command
to obtain incremented values of data,
writing the modified values of data includes writing the
incremented values of data, and
sending the completion code includes sending an atomic
increment completion code to the processor.
5. The method of claim 1, where the values of data
comprise error correcting code protected data, and
where:
modifying the values of data includes modifying the
values of data and computing new error correcting code parity
bits, and
writing the modified values of data includes writing the
modified values of data and the new error correcting code parity
bits to the at least one memory chip.
Rejection on Appeal
The Examiner rejected claims 1, 3-8, 10-14, and 16-23 under
35 U.S.C. § 103(a) as being unpatentable over Machado (US 2004/0153902
Al, Aug. 5, 2004) in view of Jeddeloh (US 2010/0005238, Jan. 7, 2010)
(Final Act. 4--9).
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Grouping of Claims
Based on Appellants' arguments, we decide the appeal of claims 1, 3,
6, and 7 on the basis of representative claim 1. See 37 C.F.R.
§ 41.37(c)(l)(iv). We separately address claims 4 and 11; claims 5 and 12;
claims 8, 10, and 13; claims 14, 16, and 19; and finally, claims 17, 18, and
20-23, infra.
ANALYSIS
Rejection of Claims 1, 3, 6 and 7 under 35 U.S.C. § 103
Issue 1: Whether the Examiner erred in rejecting claims 1, 3, 6, and 7
as being unpatentable over Machado and Jeddeloh because neither discloses
or suggests the limitations in independent claim 1 of:
the plurality of memory chips and the logic chip being on
a single die of the memory architecture,
the plurality of memory chips being included in a stack
of memory chips on the single die.
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner has erred. Further, we have reviewed the
Examiner's response to claims 1-8 that has been argued by the Appellants.
App. Br. 11-19. With regard to claims 1, 3, 6, and 7, we adopt as our own
( 1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken and (2) the reasons set forth by the Examiner in
the Examiner's Answer in response to Appellants' Appeal Brief. We concur
with the conclusions reached by the Examiner. We highlight and address
specific findings and arguments for emphasis as follows.
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Appellants argue:
Although, this section of JEDDELOH et al. identifies a
logic die 202 and states that"[ m ]ultiple memory arrays (e.g.,
the memory array 203) are fabricated onto each of a plurality of
dies (e.g., the die 204)," this section of JEDDELOH et al. does
not disclose or suggest that the logic die 202 is also on the die
204. Instead, and in stark contrast, Fig. 2 of JEDDELOH et al.
clearly indicates that the die 204 and the logic die 202 are
separate.
App. Br. 9-10 (emphasis omitted).
The Examiner finds, and we agree, that the labeled "dies" correspond
to the claimed "chips" (Ans. 5). Thus, Figure 2 of Jeddeloh teaches a
plurality of memory chips and the logic chip being on a single die. In
particular, the Examiner states, "Jeddeloh's in figure 2 teaches the same
stacked-die with memory chips and logic chip in an alternate design
configuration to share common control logic" (Id. (emphases ours)). See
also In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009) (a reference does
not have to satisfy an ipsissimis verbis test to disclose a claimed element).
Appellants have not provided an explicit definition of the term "die"
in their Specification. The Specification discloses:
Memory architecture of a memory device is provided that
includes one or more memory chips (e.g., storage chips or
layers) and a separate logic chip (e.g., logic specific chip or
layer) on a single die (e.g., die-split memory, such as a stacked
memory or a side-split memory).
Spec. i-f 12 (emphases ours).
Thus, according to Appellants' Specification, a chip may correspond
to a layer, and a die may correspond to a stack of memories or layers.
Although this disclosure is not limiting of the claimed invention, it provides
context for which the terms "chip" and "die" are interpreted. The stacked
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memory represented in Appellants' drawing of Figure 1 A also supports the
representation of the memory chips and the logic chip as layers of a same
stacked die structure. This is similar to Figure 2 of Jeddeloh having memory
layers 204 labeled as "dies," along with a logic layer 202, all part of the
same stacked structure that the Examiner interprets as a single stacked "die"
(Final Act. 5; Ans. 5).
For the foregoing reasons, we concur with the Examiner that Jeddeloh
teaches the claim 1 limitations discussed in relation to issue 1.
Issue 2: Whether the Examiner erred in rejecting claims 1, 3, 6, and 7
as being unpatentable over Machado and Jeddeloh because neither discloses
or suggests the limitations independent in claim 1 of:
transferring, by the logic chip and based on the request,
the values of data from the at least one memory chip to the
logic chip;
modifying, via the logic chip and based on the request,
the values of data to obtain modified values of data; and
writing, from the logic chip and to the at least one of
memory chip, the modified values of data.
The Examiner relies on the combination of Machado and J eddeloh to
teach these limitations (Final Act. 5-6; Ans. 6). The Examiner finds
Machado teaches reading, modifying and writing via a logic system to and
from a flash memory during error correction coding (Ans. 6). Appellants
contend Machado does not teach or suggest a logic chip. Appellants state:
In fact, this section of MACHADO et al. does not
disclose or suggest any logic chip. Instead, this section of
MACHADO et al. refers to an "internal background task [that]
may be included in the memory" (emphasis added).
App. Br. 15.
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However, we note the Examiner has relied on Jeddeloh to teach the
logic chip (Final Act. 5; Ans. 5). The Examiner relied upon Machado to
teach the read, modify and write operations between a logic system and a
memory. One cannot show nonobviousness by attacking references
individually when the rejection is based on a combination of references. In
re Keller, 642 F.2d 413, 425 (CCPA 1981). Each reference cited by the
Examiner must be read, not in isolation, but for what it fairly teaches in
combination with the prior art as a whole. See In re Merck & Co., Inc., 800
F.2d 1091, 1097 (Fed. Cir. 1986). For these reasons, we find unpersuasive
Appellants' argument that Machado does not teach a logic chip when
Jeddeloh was cited to teach this. The Examiner's proposed combination is
reasonable with some rational underpinning based on the need for a small
size high density memory packaging system (Final Act. 6).
For the foregoing reasons, we agree with the Examiner that Jeddeloh
teaches the limitations discussed in relation to issue 2 and consequently we
sustain the Examiner's rejection of representative claim 1.
Rejection of Claims 4 and 11under35 U.S.C. § 103
Issue 3: Whether the Examiner erred in rejecting claim 4 and 11 as
being unpatentable over Machado and Jeddeloh because neither discloses or
suggests the limitations in dependent claim 4 of:
modifying the values of data includes modifying the
values of data by incrementing the values of data by an
increment amount specified by the atomic increment command
to obtain incremented values of data,
writing the modified values of data includes writing the
incremented values of data, and
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sending the completion code includes sending an atomic
increment completion code to the processor.
In reference to paragraphs 62 and 114--116 of Machado, Appellants
argue, "this section [sic] of MACHADO et al does not disclose or suggest
that one bit corrections or two-bit corrections include receiving 'an atomic
increment command,' as recited in claim 4." App. Br. 18. The Examiner
finds, and we agree, the "auto correct" taught by Machado corresponds to
the "atomic increment command" because both perform a
"read/modify/write" function (Ans. 7).
We note Appellants have not provided an explicit definition of the
term "atomic increment command" in their Specification. The Specification
discloses:
For example, an atomic increment command may be provided
by memory architecture 100 that accepts an address and an
increment amount. Upon receiving the command, memory
architecture 100 can load the value from the specified address,
can increment the value by the increment amount, and can
store a modified value back to the memory, while ensuring that
no other requests (read, write, or another atomic read-modify-
write operation) access the same memory location at the same
time.
Spec. i-f 44 (emphases ours).
Thus, the atomic increment command is associated with a read-
modify-write operation. Based on our review of Machado (i-fi-f 62 and 114--
116) and consistent with the Examiner's stated position that reading is done
from a specified address (Ans. 7), we interpret the claim language "atomic
increment command" using the broadest reasonable interpretation consistent
with Appellants' disclosure - to comprise reading, modifying and writing
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one-bit to and from memory. See Jn re Morris, 127 F.3d 1048, 1054 (Fed.
Cir. 1997).
We are also not persuaded by Appellants' argument in the Reply Brief
(page 7) that "the Examiner cannot allege that auto correct, of MACHADO
et al., is an atomic increment command without providing any evidence
(e.g., references) that the auto correct, of MACHADO et al., is in fact an
atomic increment command," because claim 4 does not preclude the atomic
increment command from being performed by auto correcting, or modifying
the data by correcting one-bit error incrementing memory values during the
process.
Therefore, on this record, in light of Appellants' Specification, and by
a preponderance of the evidence, we sustain the Examiner's rejection of
claim 4 as well as claim 11, which was not argued separately (App. Br. 27).
Rejection of Claims 5 and 12 under 35 U.S.C. § 103
Issue 4: Whether the Examiner erred in rejecting claim 5 and 12 as
being unpatentable over Machado and Jeddeloh because neither discloses or
suggests the limitations in dependent claim 5 of:
where the values of data comprise error correcting code
protected data, and
where:
modifying the values of data includes modifying the
values of data and computing new error correcting code parity
bits, and
writing the modified values of data includes writing the
modified values of data and the new error correcting code parity
bits to the at least one memory chip.
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As to Appellants' contention that paragraph 62 of Machado does not
teach "error correcting code protected data" (App. Br. 22), Appellants admit
that Machado teaches "a serial flash memory 100 is provided with an
integrated error correction coding ('ECC') system 140," yet Appellants do
not explain why it would not have been obvious to one skilled in the art to
provide error correcting code protected data. Likewise, Appellants note
Machado teaches "check bits 220 form an ECC codeword 200" (Reply Br.
8), yet do not explain why it would not have been obvious to one skilled in
the art that the check bit correspond to an error correcting code parity bit.
We agree with the Examiner that error correcting code protected data
is taught by Machado because a group of data bits is protected by an error
correcting code system (Final Act. 7; Ans. 8 (citing Machado i-f 8)). The
Examiner additionally cites paragraphs 71 and 94 (Ans. 8-9) to explain how
the error correcting code taught by Machado corresponds to the above claim
limitations. Again, we interpret the terminology "new error correcting code
parity bits" and "error correcting code protected data" using the broadest
reasonable interpretation consistent with Appellants' disclosure to comprise
error correcting codewords that are encoded and mapped to protect data bits
(Id.). Appellants do not point to anything in the claims or Specification or
present persuasive evidence or argument that precludes this interpretation.
See E-Pass Techs., Inc. v. 3Com Corp., 343 F.3d 1364, 1369 (Fed. Cir.
2003) (limitations not explicit or inherent in the language of a claim cannot
be imported from the specification); In re Van Geuns, 988 F.2d 1181, 1184
(Fed. Cir. 1993) (although the claims are interpreted in light of the
specification, limitations from the specification are not read into the claims).
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For the reasons stated supra, we find Appellants' arguments
unavailing regarding the limitations of claim 5. We accordingly sustain the
Examiner's rejection of claim 5 as well as claim 12, which was not argued
separately (App. Br. 28).
Rejection of Claims 8, 10, and 13 under 35 U.S.C. § 103
Issue 5: Whether the Examiner erred in rejecting claim 8, 10, and 13
as being unpatentable over Machado and Jeddeloh because neither discloses
or suggests the limitations in independent claim 8 of:
one or more memory layers on the single die; and
a logic layer,
the logic layer being vertically stacked, on the single die,
with the one or more memory layers.
Although Appellants contest the Examiner groups claims 8, 14, and
20 into the same rejection as that of claim 1, in contesting claim 8
ii~ppellants provide no ne\'l/ arguments \'l1ith respect to those regarding claim
1 (App. Br. 25). Appellants' additional argument of the logic layer "being
vertically stacked" on the single die (Reply Br. 12), is also interpreted in
light of the above discussion over the meaning of "die" as referring to a
structure of "stacked layers" which may be considered vertical.
Accordingly, we sustain the Examiner's rejection of claim 8 as well as
claims 10 and 13, which were not argued separately (App. Br. 24), for the
same reasons discussed regarding claim 1 supra.
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Rejection of Claims 14, 16, and 19 under 35U.S.C.§103
Issue 6: Whether the Examiner erred in rejecting claim 14, 16, and 19
as being unpatentable over Machado and Jeddeloh because neither discloses
or suggests the limitation in independent claim 14 of:
the logic layer being horizontally separated from the
memory layers on the single die.
As to Appellants' above contention, we disagree with Appellants'
arguments (App. Br. 29-30; Reply Br. 13), because Appellants do not define
"horizontally separated," in a manner that would preclude the Examiner's
interpretation (Ans. 10) of the structure shown in Figure 2 and described in
paragraph 13 of J eddeloh as representing horizontal separation.
Further, we are not persuaded the Examiner has erred because
Appellants provide no persuasive evidence of the alleged error. Specifically,
Appellants provide no persuasive evidence or argument regarding how
Jeddeloh's logic layer of Figure 2 is not horizontally separated. Rather,
Appellants merely provide conclusory remarks that Jeddeloh's Figure 2 is
different from what is claimed. Reply Br. 13. It is well settled that mere
attorney's arguments and conclusory statements, which are unsupported by
factual evidence, are entitled to little probative value. In re Geisler, 116
F.3d 1465, 1470 (Fed. Cir. 1997); In re De Blauwe, 736 F.2d 699, 705 (Fed.
Cir. 1984). Attorney argument is not evidence. In re Pearson, 494 F.2d
1399, 1405 (CCPA 1974). Nor can such argument take the place of
evidence lacking in the record. Meitzner v. Mindick, 549 F.2d 775, 782
(CCP A 1977).
The remainder of Appellants' arguments surrounding claim 14 are
discussed supra in relation to claim 1.
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Therefore, we are unpersuaded of error in the Examiner's
interpretation of claim 14, as well as claims 16 and 19, which were not
argued separately (Reply Br. 13-14).
Rejection of Remaining Claims 17, 18, and 20--23 under 35 U.S.C. § 103
Appellants have not presented separate arguments beyond those
already discussed, in addressing claims 17, 18, and 20-23 (App. Br. 31-37;
Reply Br. 14--15). We accordingly sustain the Examiner's rejections of
claims 17, 18 and 20-23.
CONCLUSION
The Examiner did not err in rejecting claims 1, 3-8, 10-14, and 16-23
under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Machado and J eddeloh.
DECISION
The Examiner's rejection of claims 1, 3-8, 10-14, and 16-23 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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