Ex Parte Lin et al

Patent Trial and Appeal Board

Feb 13, 2014

11594068 (P.T.A.B. Feb. 13, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte WEN-JUI LIN, HSIEN-CHUN CHANG,
YI-SHU CHANG, and WEN-CHE WU
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Appeal 2011-009169
Application 11/594,068
Technology Center 2100
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Before JOHNNY A. KUMAR, LARRY J. HUME, and
IRVIN E. BRANCH, Administrative Patent Judges.

BRANCH, Administrative Patent Judge.

DECISION ON APPEAL
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STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Non-Final Rejection of claims 1–17. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.
Illustrative Claim
Appellants’ invention relates to updating parameters on a controller
that includes an embedded non-volatile memory. Abstract.
Claim 1, reproduced below with the disputed limitations italicized, is
illustrative of the claimed subject matter:
1. An apparatus for updating at least one parameter,
comprising:
an embedded non-volatile memory having a program
code block being defined by a first address range for storing a
program code and a data block being defined by a second
address range for storing at least one parameter;
an embedded volatile memory for storing data;
a memory controller, which is directly coupled to the
embedded non-volatile memory and the embedded volatile
memory, for controlling reading/writing of the embedded non-
volatile memory and the embedded volatile memory through a
first interface signal; and
a processor coupled to the memory controller through a
second interface signal, which includes an address signal, a data
signal and a control signal, the processor executing the program
code stored in the program code block, wherein the processor is
configured to have read-only access to memory locations in the
first address range of the non-volatile memory and read/write
access to memory locations in the second address range of the
non-volatile memory;
wherein the processor writes the at least one parameter
into the data block of the embedded non-volatile memory.
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Rejections
The Examiner rejected:
Claims 1–9 and 12–15 under 35 U.S.C. § 103(a) as unpatentable over
Applicants’ Admitted Prior Art (“AAPA” (Spec. pp. 1–2; Figs. 1, 2)) and
Xie (US 2006/0248267 A1) (Ans. 4–9); and
Claims 10, 11, 16, and 17 under 35 U.S.C. § 103(a) as unpatentable
over AAPA, Xie, and Bruce (US 6,000,006) (Ans. 10–12).

ISSUES
Appellants’ arguments raise the following issues:
1) Whether the combination of AAPA and Xie teach or suggest
“an embedded non-volatile memory having a program code block being
defined by a first address range for storing a program code and a data block
being defined by a second address range for storing at least one parameter”
and “wherein the processor is configured to have read-only access to
memory locations in the first address range of the non-volatile memory and
read/write access to memory locations in the second address range of the
non-volatile memory” as recited in claim 1;
2) Whether AAPA and Xie were properly combined; and
3) Whether the Examiner’s rejection of claims 10, 11, 16, and 17
is proper.

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments in the Appeal Brief (“App. Br.” filed Feb. 14, 2011) and Reply
Brief (“Reply Br.” filed May 11, 2011). We refer to the Briefs and the
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Answer (“Ans.” mailed Mar. 29, 2011) for the respective positions of
Appellants and the Examiner.
We agree with the Examiner and adopt as our own (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken and (2) the reasons set forth by the Examiner in the Examiner’s
Answer in response to Appellants’ Appeal Brief. See Ans. 4–18. We
highlight and address specific findings for emphasis as follows.

35 U.S.C. § 103 Rejection of Claim 1 Over AAPA and Xie
Appellants argue AAPA “does not teach that the processor has read-
only access to only a portion (define by a first address range) of the
embedded non-volatile memory, while having read-write access to another
portion (define by a second address range) of the embedded non-volatile
memory.” App. Br. 5–6. Appellants further argue Xie “doesn’t teach the
specified address ranges of the memory blocks being stored in non-volatile
memory, as required by the claims [and in] fact, it teaches just the opposite,
by noting that the settings in the configuration register are lost if the flash
device 100 is powered down.” Id. at 7. Appellants also argue “the
combination of AAPA and Xie is improper [because] the Office Action
failed to cite a motivation for combining Xie with AAPA” (id. at 9) and “the
alleged rationale for combining the references is merely an improper
conclusory statement that embodies clear and improper hindsight rationale”
(id. at 11). See also id. at 9–12.
In the rejection of claim 1, for the disputed limitations the Examiner
cites AAPA and Xie. Ans. 4–7. Xie teaches “an embedded non-volatile
memory” (¶ 2 (flash memory device)) storing “program code” and “at least
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one parameter” (¶ 58 (code and user configuration settings)) in different
address ranges (id. (sector 0 for user data and everything else for code). The
processor has read-only access to the code section and read/write access to
the data block (id. (“write protect all of the memory array 110 except
Sector 0”)). Accordingly, we are not persuaded the Examiner erred in
finding the combination of AAPA and Xie teaches or suggests the disputed
limitations of “an embedded non-volatile memory having a program code
block being defined by a first address range for storing a program code and a
data block being defined by a second address range for storing at least one
parameter” and “wherein the processor is configured to have read-only
access to memory locations in the first address range of the non-volatile
memory and read/write access to memory locations in the second address
range of the non-volatile memory” as recited in claim 1.
Moreover, the combination of familiar elements according to known
methods is likely to be obvious when it does no more than yield predictable
results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). If a
technique has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its actual application is
beyond his or her skill. KSR, 550 at 417. Thus, when considering
obviousness of a combination of known elements, the operative question is
“whether the improvement is more than the predictable use of prior art
elements according to their established functions.” Id.
Here, the Examiner has shown all elements to exist in the prior art.
Appellants have not presented sufficient argument or evidence to persuade
us that Appellants’ invention is more than the predictable use of these
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elements or that combining them would have been beyond the skill of an
ordinarily skilled artisan. Accordingly, Appellants’ arguments that the
Examiner has improperly combined AAPA and Xie (App. Br. 9–12) are
unavailing of error because we find the Examiner has met his burden under
KSR by finding the cited prior art combination would be obvious “[for] the
purpose of providing a protection scheme for the flash memory . . . thereby
preventing erasing or rewritten wrong area and/or preventing corrupting
code portion of the memory array.” Ans. 7, 15 (citing Xie ¶¶ 3 and 4). We
therefore sustain the Examiner’s rejection of claim 1, the Examiner’s
rejection of claim 12, which Appellants argue on the same grounds (App. Br.
at 8–9), and the Examiner’s rejection of claims 2–9 and 13–15, which
Appellants do not separately argue.

35 U.S.C. § 103 Rejection of Claims 10, 11, 16,
and 17 Over AAPA, Xie, and Bruce
Appellants argue the Examiner’s rejection of claims 10, 11, 16, and 17
is improper because the motivation for combining AAPA, Xie, and Bruce is
improper (App. Br. 12–14), and because Bruce fails to disclose the claimed
features (id. at 14–17). We disagree with Appellants for the reasons stated
by the Examiner (Ans. 10–12, 16–18). We adopt the Examiner’s findings
and conclusions. For emphasis we note that Appellants have not presented
sufficient argument or evidence to persuade us of error in the Examiner’s
conclusion
it would have been obvious to one having ordinary skill in the
art at the time the invention was made to incorporate . . . the
processor [storing] an address translation table, which records
an address currently used at the data block of the flash memory,
in the embedded volatile memory as taught by Bruce into the
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combined invention of AAPA and Xie for the purpose of
increasing life of non-volatile memory by decreasing a wearing
level.
Ans. 11 (citing Bruce col. 2, ll. 53–59; col. 3, ll. 30–40). Accordingly, we
sustain the Examiner’s rejection of claims 10, 11, 16, and 17.

CONCLUSIONS
On the record before us, we conclude: the Examiner has not erred in
rejecting claims 1–9 and 12–15 under 35 U.S.C. § 103(a) as unpatentable
over AAPA and Xie; and the Examiner has not erred in rejecting claims 10,
11, 16, and 17 under 35 U.S.C. § 103(a) as unpatentable over AAPA, Xie,
and Bruce.

DECISION
For the above reasons, the Examiner’s rejection of claims 1–17 is
affirmed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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