Ex Parte Lin et al

Patent Trial and Appeal Board

Mar 17, 2016

12814515 (P.T.A.B. Mar. 17, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/814,515 06/14/2010 Kuan-Yi Lin
27765 7590 03/21/2016
NORTH AMERICA INTELLECTUAL PROPERTY CORPORATION
P.O. BOX506
MERRIFIELD, VA 22116
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
MTKP1038USA 9504
EXAMINER
JEBARI, MOHAMMED
ART UNIT PAPER NUMBER
2482
NOTIFICATION DATE DELIVERY MODE
03/21/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
Patent.admin.uspto.Rcv@naipo.com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte KUAN-YI LIN, YANG-TSE LI, and YU-NIEN CHIEN
Appeal2014-005040
Application 12/814,515
Technology Center 2400
Before ALLEN R. MacDONALD, CARLA M. KRIVAK, and
MICHAEL M. BARRY, Administrative Patent Judges.
MacDONALD, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-005040
Application 12/814,515
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1-15, 18, and 21-24, which constitute all the
claims pending in this application. Claims 16, 17, 19, and 20 have been
cancelled. We have jurisdiction under 35 U.S.C. § 6(b ).
Exemplary Claims
Exemplary claims 1 and 15 under appeal read as follows (emphasis
added):
1. A video processing apparatus, comprising:
a video decoder, for decoding an encoded video input to
generate a video input with a source video format;
a storage device, coupled to the video decoder, for
buffering the video input generated from the video decoder; and
a video output device, coupled to the storage device, for
outputting a video output to a display device by reading the
video input buffered in the storage device during at least one
data scanning clock period, each data scanning clock period
being set according to a time period between two successive
pulses of a vertical synchronization signal referenced for actual
video display, wherein the video output has a display video
format satisfying a display capability of the display device, and
the source video format and the display video format are
three-dimensional (3D) video formats different from each
other.
15. A video processing apparatus, comprising:
a video decoder, for decoding an encoded video input to
generate a first video input with a source video format;
a first storage device;
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Application 12/814,515
a storage control device, coupled between the video
decoder and the first storage device, for generating a second
video input with a display video format to the first storage
device according to the first video input with the source video
format; and
a video output device, coupled to the first storage device,
for outputting a video output to a display device according to
the second video input buffered in the first storage device,
wherein the video output has the display video format
satisfying a display capability of the display device, and the
source video format and the display video fomlat are three-
dimensional (3D) video formats different from each other;
wherein the storage control device comprises:
a second storage device, coupled to the video decoder,
for buffering the first video input generated from the video
decoder; and
a storage address re-mapping device, coupled between
the first storage device and the second storage device, for re-
mapping storage addresses of the first video input buffered in
the second storage device to the first storage device and
accordingly storing the second i'ideo input in the first storage
device, wherein the first video input in the second storage
device is stored into the first storage device at re-mapped
storage addresses to serve as the second video input.
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Application 12/814,515
Rejections
1. The Examiner rejected claims 1-14, 22, and 24 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Matsui et al. (US
2003/0128273 Al; July 10, 2003) ("Matsui"), Ha (US 2006/0177123 Al;
Aug. 10, 2006), and Tomita (US 2002/0008906 Al; Jan. 24, 2002). 1 Final
Act. 5-11.
2. The Examiner rejected claims 21and23 under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Matsui, Ha, Tomita, and Doi
(US 6,278,418 Bl; Aug. 21, 2001).2 Final Act. 15-16.
3. The Examiner rejected claims 15 and 18 under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Matsui, Ha, Tokumo et al.
(US 2008/0106550 Al; May 8, 2008) ("Tokumo"), and Colpo et al. (US
2003/0018873 Al; Jan. 23, 2003) ("Colpo"). 3 Final Act. 11-15.
Appellants' Contentions
1. Appellants contend that the Examiner erred in rejecting claim 1
under 35 U.S.C. § 103(a) because:
Matsui discloses that the input video data and the displayed
video data have different formats (FIG. 7 and paragraphs
[0094]-[0095]), but does not teach or suggest referring a
1 Separate patentability is not argued for claims 2-14, 22, and 24. See App.
Br. 6-8. Except for our ultimate decision, these claims are not discussed
further herein.
2 Separate patentability is not argued for claims 21 and 23. Rather,
Appellants merely references claims 1 and 8. See App. Br. 10. Thus, the
rejection of these claims turns on our decision as to the rejection of claims 1
and 8. Except for our ultimate decision, claims 21 and 23 are not discussed
further herein.
3 Separate patentability is not argued for claim 18. See App. Br. 8-10.
Except for our ultimate decision, this claim is not discussed further herein.
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Appeal2014-005040
Application 12/814,515
vertical synchronization signal to read a video data which
does not comply with a 3D display format. With regard to
Tomita's disclosure, the video data stored in VRAM (56)
already complies with the 3D display format of the display
(55).
App. Br. 6-7.
2. Appellants contend that the Examiner erred in rejecting claim 1
under 35 U.S.C. § 103(a) because:
The appellant wishes to emphasize that what Tomita discloses
in FIGs. 9A-9B is the conventional display operation which
sequentially transmits frames in VRAM (56) to the display
apparatus according to timing of the vertical synchronization
signal. Hence, the vertical synchronization signal mentioned by
Tomita is merely used to control the display timing of each
frame in VRAM (56), rather than the timing of reading frame
data from VRAM (56).
Reply Br. 4.
3. Appellants also contend that the Examiner erred in rejecting claims
15 and 18 under 35 U.S.C. § 103(a) because, contrary to the Examiner's
construction, "the claimed storage address re-mapping operation does
change the format of the stored data." App. Br. 9.
Issues on Appeal
Did the Examiner err in rejecting claims 1 and 15 as obvious over the
cited prior art?
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
Appeal Brief arguments that the Examiner has erred.
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Application 12/814,515
As to Appellants' above contention 3 covering claims 15 and 18, we
agree. In response to Appellants' argument, Examiner asserts:
Based on the language of claims 15 and 18, the storage
address re-mapping device does not change the format of the
stored data. It simply re-maps storage addresses of video data
in one memory to another one and stores video data from the
one memory to the another one, and that is what Colpo
discloses.
Ans. 19. Although no one clause of claim 15 shows the argued limitation,
we conclude the limitation is set forth in claim 15 when the claim is taken as
a whole. Claim 15 recites "afirst video input with a source video format,"
"generating a second video input with a display video format," and "the
source video format and the display video format are three-dimensional (3D)
video formats different from each other." (Emphases added). Further, claim
15 recites "re-mapping storage addresses of the first video input buffered in
the second storage device to the first storage device and accordingly storing
the second video input in the first storage device .... " (Emphases added).
Collectively, these limitations require that the "re-mapping operation does
change the format of the stored data," as argued. See App. Br. 8-9.
As to Appellants' above contention 1, we disagree for the reasons set
forth by the Examiner (Ans. 18-19) because Appellants' argued limitation
("which does not comply with a 3D display format") is not required by the
language of claim 1.
As to Appellants' above contention 2, contrary to Appellants'
statement ("The appellant would like to address the points made by the
Examiner in the Examiner's Answer dated 01/17/2014. "), Appellants present
for the first time a new argument against the rejection of claim 1.
Appellants' previous mention of the "reading" claim limitation was as part
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Application 12/814,515
of a restatement of entire steps from claim 1, and as such was not a
particularized argument directed to the "reading" limitation. See App. Br.
6-8.
In the absence of a showing of good cause by Appellants, we decline
to consider an argument raised for the first time in the Reply Brief. This is
because, as the Examiner has not been provided a chance to respond, and in
the absence of a showing of good cause by Appellants, these arguments are
deemed waived. See 37 C.F.R. § 41.41(b )(2); Ex parte Nakashima, 93
USPQ2d 1834, 1837 (BP AI 2010) (informative) (explaining that arguments
and evidence not timely presented in the principal Brief, will not be
considered when filed in a Reply Brief, absent a showing of good cause
explaining why the argument could not have been presented in the Principal
Brief); Ex parte Borden, 93 USPQ2d 1473, 1477 (BPAI 2010) (informative)
("[p]roperly interpreted, the Rules do not require the Board to take up a
belated argument that has not been addressed by the Examiner, absent a
showing of good cause."). Appellants have provided no such showing of
good cause in the record before us.
In this case, even if we consider Appellants' above contention 2, the
argument does not convince us the Examiner erred. Appellants are mistaken
in arguing that "Tomita is merely used to control the display timing of each
frame in VRAM ( 5 6), rather than the timing of reading frame data from
VRAM (56)." Instead, an artisan would understand that the timing of
reading from VRAM (56) in Tomita coincides with the display timing of
VRAM (56). See Tomita at paragraph 78 ("the picked up picture data for a
left eye of one frame are read out from the memory sections 56a and 56b of
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Application 12/814,515
the VRAM 56, and the picked up picture for a right eye and the picked up
picture for a left eye are displayed alternately.") (Emphasis added).
CONCLUSIONS
(1) The Examiner has not erred in rejecting claims 1-14 and 21-24 as
being unpatentable under 35 U.S.C. § 103(a).
(2) Appellants have established that the Examiner erred in rejecting
claims 15 and 18 as being unpatentable under 35 U.S.C. § 103(a).
(3) Claims 15 and 18 have not been shown to be unpatentable.
(4) Claims 1-14 and 21-24 are not patentable.
DECISION
The Examiner's rejections of claims 1-14 and 21-24 are affirmed.
The Examiner's rejection of claims 15 and 18 as being unpatentable
under 35 U.S.C. § 103(a) is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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