Ex Parte Lin

Board of Patent Appeals and Interferences

Aug 22, 2012

09943242 (B.P.A.I. Aug. 22, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte WEN LIN
____________

Appeal 2010-000504
Application 09/943,242
Technology Center 2100
____________

Before KRISTEN L. DROESCH, KALYAN K. DESHPANDE and
DAVID M. KOHUT, Administrative Patent Judges.

DROESCH, Administrative Patent Judge.
DECISION ON APPEAL

Appeal 2010-000504
Application 09/943,242

2
STATEMENT OF THE CASE
Appellant seeks review under 35 U.S.C. § 134(a) of a final rejection
of claims 1-3, 5, 7, 10, 12, 17-22 and 32.
1
We have jurisdiction under 35
U.S.C. § 6(b). We AFFIRM-IN-PART.
BACKGROUND
Appellant’s disclosed invention relates to software, systems and
methods for efficiently implementing mass storage control in systems with
integrated mass storage. Spec. 1.
Claim 1 is illustrative and is reproduced below (disputed limitation in
italics):
1. A computing system comprising:
a processor having a data/control bus interface;
a data/control bus implementing one or more device
communication channels;
a mass storage device having an interface for
communicating mass storage transactions;
a data memory coupled to and shared by both the
processor and the mass storage device; and
a bus controller having a memory interface coupled to
the data memory and a mass storage interface coupled to the
mass storage device’s interface without an intermediary mass
storage controller and operable to conduct mass storage
transactions between the data memory and the mass storage
device and to arbitrate access to memory locations within the
data memory between the data/control bus and the mass storage
device.

1
Claims 4, 6, 8, 9, 11, 13-16 and 23-31 have been cancelled.

Appeal 2010-000504
Application 09/943,242

3
Rejections
Claims 1-3, 5 and 21 stand rejected under 35 U.S.C. § 102(e) as
anticipated by Hunsaker (U.S. 2003/0037198 A1).
Claims 1, 12 and 20 stand rejected under 35 U.S.C. § 102(e) as
anticipated by Zaidi (U.S. 6,601,126 B1).
Claims 1 and 20
2
stand rejected under 35 U.S.C. § 102(e) as
anticipated by Moriarty (U.S. 6,128,669).
Claims 1 and 19 stand rejected under 35 U.S.C. § 102(e) as
anticipated by Ellison (U.S. 2002/0144121 A1).
Claims 17 and 18 stand rejected under 35 U.S.C. § 102(e) as
anticipated by Houston (U.S. 6,493,656 B1)
Claims 7, 10 and 32 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Hunsaker, Zaidi, Moriarty, or Houston in view of
Operating Systems: Design and Implementation (“Tanenbaum”).
Claim 22 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Hunsaker and Yiu (U.S. 2003/0181205 A1).
ISSUES
Did the Examiner err in finding that Hunsaker, Ellison, Zaidi,
Moriarty or Houston anticipates the claimed invention?
Did the Examiner err in determining that the combination of
Hunsaker, Ellison, Zaidi, Moriarty or Houston with Tanenbaum renders
obvious the invention of claim 32?

2
The Final Office Action, Appeal Brief and Answer indicate that claim 14
has been rejected as anticipated by Moriarty. However, claim 14 has been
cancelled.

Appeal 2010-000504
Application 09/943,242

4
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellant’s
arguments in the Appeal Brief presented in response to the Final Office
Action. We disagree with Appellant’s conclusions. We highlight and address
specific findings and arguments for emphasis as follows.
Rejection of claims 1-3, 5 and 21 as anticipated by Hunsaker
The Examiner finds, referring to Hunsaker’s Figure 1 below, that
Hunsaker describes a bus controller (i.e., input/output controller hub (ICH)
150) having a memory interface coupled to the data memory (i.e., system
memory 140) because the ICH 150 is coupled to the system memory 140 via
memory controller hub (MCH) 130, and a mass storage interface coupled to
the mass storage device’s 170 interface without an intermediary mass
storage controller, because ICH 150 is coupled directly to mass storage
device 170 without anything in between. Ans. 4-5.
Hunsaker’s Figure 1 is below:

Figure 1 depicts a computer system.

Appeal 2010-000504
Application 09/943,242

5
Appellant argues that “neither Hunsaker’s MCH 130 nor the ICH 150
has both an interface coupled to the data memory and a mass storage
interface so these devices cannot teach the bus controller of claim 1.” Br. 6.
Appellant further argues that the Office appears to be impermissibly
combining the two controller hubs (MCH 130 and ICH 150) into a single
controller or device. Br. 6-7. We are unpersuaded by Appellant’s arguments
as they are not commensurate in scope with the claim language. The plain
language of claim 1 does not require the bus controller to be implemented as
a single device.
Appellant further argues that claim 1 requires the bus controller to
have a memory interface coupled to the data memory, which is not taught by
Hunsaker because Hunsaker describes a connection via another controller
(i.e., via MCH 130). Br. 7-8. However, Appellant’s arguments are
unpersuasive because they are not commensurate in scope with the claim
language. The plain language of claim 1 does not require the bus controller
to have a memory interface directly coupled to the data memory (i.e.,
without any intermediary devices or interfaces).
Appellant also argues that because Hunsaker does not discuss a mass
storage interface for ICH 150 coupled to the mass storage device’s interface,
Hunsaker does not explicitly teach or suggest the direct interface required by
claim 1. Br. 8. We are unpersuaded by Appellant’s argument since
Hunsaker’s Figure 1 depicts direct communication (i.e., the arrow) between
the ICH 150 and the mass storage device 170. The direct communication
between the ICD 150 and mass storage device 170 requires respective

Appeal 2010-000504
Application 09/943,242

6
interfaces at the ICH 150 and mass storage device 170 in order to enable the
direct communication between the ICH and the mass storage device 170.
Last, Appellant argues that Hunsaker does not describe that the ICH
150 is configured to “conduct mass storage transactions between the data
memory and the mass storage device.” Br. 8. Appellant’s argument is
unpersuasive since it focuses on the function of the structure recited in claim
1 -- “operable to conduct mass storage transactions between the data
memory and the mass storage device.” When the structural limitations are all
found in the prior art, the absence of a disclosure in the prior art relating to
function does not defeat the finding of anticipation or determination of
obviousness. “It is well settled that the recitation of a new intended use for
an old product does not make a claim to that old product patentable.” In re
Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997) (“structure will be used to
dispense popcorn does not have patentable weight if the structure is already
known, regardless of whether it has ever been used in any way in connection
with popcorn”). Appellant does not meaningfully explain why, contrary to
the Examiner’s findings, Hunsaker’s structure (i.e., ICH 150 and MCH 130)
is incapable of operating to conduct mass storage transactions between the
data memory (i.e., system memory 140) and the mass storage device 170.
For all these reasons, we sustain the Examiner’s rejection of claims 1-
3, 5 and 21 as anticipated by Hunsaker.
Claims 1 and 19 anticipated by Ellison
Similar to the Examiner’s rejection based on Hunsaker, the Examiner
finds, referring to Ellison’s Figure 1C below, that Ellison describes a bus
controller (i.e., input/output controller hub (ICH) 150) having a memory

Appeal 2010-000504
Application 09/943,242

7
interface coupled to the data memory (i.e., system memory 140) because the
ICH 150 is coupled to the system memory 140 via memory controller hub
(MCH) 130, and a mass storage interface coupled to the mass storage
device’s 170 interface without an intermediary mass storage controller,
because ICH 150 is coupled directly to mass storage device 170 without
anything in between. Ans. 7-8.
Ellison’s Figure 1C is below:

Figure 1C depicts a platform.
Appellant presents substantially identical arguments to those
addressing the rejection based on Hunsaker. Compare Br. 11-12 with Br. 6-
8. For the same reasons as those addressing the rejection of claims 1-3, 5 and
21 as anticipated by Hunsaker, we sustain the Examiner’s rejection of claims
1 and 19 as anticipated by Ellison.
Claims 1, 12 and 20 anticipated by Zaidi
Referring to Zaidi’s Figure 28 reproduced below, the Examiner finds
that Zaidi describes a bus controller (i.e., bridge and MAC (Memory Access

Appeal 2010-000504
Application 09/943,242

8
Controller)) having a memory interface coupled to the data memory (i.e.,
DRAM (Dynamic Random Access Memory)) because the MAC is coupled
to the DRAM, and a mass storage interface coupled to the mass storage
device’s (i.e., DMA (Direct Memory Access) peripheral) interface without
an intermediary mass storage controller because the bridge is coupled to the
DMA peripherals via the PCI (Peripheral Component Interconnect) bus
without an intermediary controller. Ans. 6.
Zaidi’s Figure 28 is below:

Figure 28 depicts a PCI bus architecture.
Appellant first argues that Zaidi shows a computer architecture in
which a bridge device, not a data/control bus, couples various components.
Br. 9. Appellant’s argument is misplaced and unpersuasive because the
Examiner relies on the bridge and the MAC for describing the claimed bus
controller, not the bridge alone.
Appellant further argues that there is no controller coupled to the CPU
bus as called for in claim 1. Id. Appellant’s argument is unpersuasive
because it is not commensurate in scope with the claim language. The plain
language of claim 1 does not recite a CPU bus nor require a controller
coupled to a CPU bus.
Appellant also argues that Zaidi fails to show or suggest a data
memory coupled to the processor as called for in claim 1, but instead, the

Appeal 2010-000504
Application 09/943,242

9
DRAM is coupled to the memory bus (m-bus). Appellant’s argument is
unpersuasive because claim 1 does not require the data memory to be
directly coupled to the processor (i.e., without any intermediary devices or
interfaces). Zaidi describes that the data memory (i.e., DRAM) is coupled to
the processor (i.e., CPU) via the CPU bus, cache, bridge, m-bus and MAC.
Fig. 28.
Last, Appellant argues that Zaidi does not teach that the bridge or the
MAC is capable of conducting mass storage transactions between the data
memory and the mass storage device as required of the bus controller of
claim 1. Br. 9. We are unpersuaded by Appellant’s arguments as they focus
on the function of the structure -- “operable to conduct mass storage
transactions between the data memory and the mass storage device.” When
the structural limitations are all found in the prior art, the absence of a
disclosure in the prior art relating to function does not defeat the finding of
anticipation or determination of obviousness. See Schreiber, 128 F.3d at
1477. Appellant does not meaningfully explain why, contrary to the
Examiner’s findings, Zaidi’s structure (i.e., the bridge and MAC) is
incapable of operating to conduct mass storage transactions between the data
memory (i.e., DRAM) and the mass storage device (DMA peripherals).
For all these reasons, we sustain the Examiner’s rejection of claims 1,
12 and 20 as anticipated by Zaidi.
Claims 1 and 20 anticipated by Moriarty
The Examiner finds, referring to Moriarty’s Figure 1, that Moriarty
describes a bus controller (i.e., Host/PCI Bridge 106 and Memory Controller
108) having a memory interface coupled to the data memory (i.e., Memory

Appeal 2010-000504
Application 09/943,242

10
Subsystem 104) because the Host/PCI Bridge 106 is coupled to Memory
Subsystem 104, and a mass storage interface coupled to the mass storage
device’s interface without an intermediary mass storage controller because
the Host/PCI Bridge 106 is coupled to the SCSI controller 120. Ans. 7.
Moriarty’s Figure 1 is below:

Figure 1 depicts a computer system.
Appellant first argues that Moriarty shows a computer architecture in
which a bridge device is required for mass storage transactions, but does not
describe a bus controller that includes both a mass storage interface and an
interface to the data memory as required by claim 1. Br. 10. Appellant’s
argument is unpersuasive because the Examiner relies on the Host/PCI
Bridge 106 and Memory Controller 108 for describing the claimed bus
controller, not the Bridge 106 alone. Furthermore, contrary to Appellant’s
arguments (Br. 10-11), the plain language of claim 1 does not require the bus
controller to be embodied in a single device.

Appeal 2010-000504
Application 09/943,242

11
For all these reasons, we sustain the Examiner’s rejection of claims 1
and 20 as anticipated by Moriarty.
Claims 17 and 18 anticipated by Houston
The Examiner finds, referring to Houston’s Figure 1, that Houston
describes a bus controller (i.e., North Bridge 102 and South Bridge 114)
having a memory interface coupled to the data memory because the North
Bridge 102 is coupled to memory 106, and a mass storage interface coupled
to the mass storage device’s interface without an intermediary mass storage
controller because the North Bridge 102 is directly coupled to SCSI (Small
Computer System Interface) 121 and HD (Hard Disk) 122 and South Bridge
114 is directly coupled to HDs 118. Ans. 8-9.
Houston’s Figure 1 is below:

Figure 1 depicts a computer system.
Appellant argues that claim 1 requires the bus controller to interface
with the mass storage device without a mass storage controller, but that

Appeal 2010-000504
Application 09/943,242

12
Houston describes that such an intermediary storage controller would be
used with Houston’s HDs, and directs attention to controller 214 shown in
Houston’s Figure 2. Br. 13. We agree with Appellant’s argument since
Houston describes, referring to Figure 2 below, a hard disk drive 118 that
includes a disk controller and Integrated Drive Electronics (IDE) interface
214 that provides control functions to the drive. Col. 4, ll. 54-55; col. 4, l.
66-col. 5, l. 2; col. 5, ll. 27-44.
Houston’s Figure 2 is below:

Figure 2 depicts a hard disk drive storage device.
For this reason, we do not sustain the Examiner’s rejection of claims
17 and 18 as anticipated by Houston
Rejection of claims 7, 10 and 32 as obvious over Hunsaker, Zaidi, Moriarty
or Houston in view of Tanenbaum
Claims 7 and 10 depend from claim 1. Appellant argues that
Tanenbaum does not remedy the deficiencies of Hunsaker, Zaidi, Moriarty

Appeal 2010-000504
Application 09/943,242

13
or Houston regarding claim 1. Br. 13-15. Appellant does not substantively
address the limitations of claims 7 and 10. Id. For the same reasons as those
addressing the rejections of claim 1 as anticipated by Hunsaker, Zaidi, and
Moriarty, we sustain the Examiner’s rejection of claims 7 and 10 as obvious
over Hunsaker, Zaidi, or Moriarty in view of Tanenbaum.
3

Appellant argues that the Examiner does not address the additional
limitations of independent claim 32, with reference to claim 1 and does not
state a prima facie case of obviousness. Br. 15. Specifically, Appellant
argues that claim 32 additionally requires: (1) a first mass storage device
with an interface and the first mass storage device is coupled to a data
control bus; (2) a processor coupled to this same data control bus which
implements mass storage control processes to control the first mass storage
device; (3) a second mass storage device with an interface; (4) a bus
controller that has a mass storage interface coupled to the second mass
storage device’s interface; (5) data memory that is coupled to the
data/control bus; and (6) the bus controller conducts mass storage
transactions between the data memory and the second mass storage device.
Id.
We agree with the Examiner that the main difference between claim
32 and claim 1 is the additional limitation of the “first mass storage device”.
Ans. 18. The Examiner finds that each of the primary references show more
than one mass storage device, noting elements 172, 174, 176 and other PCI
peripherals in Hunsaker’s Figure 1 and Ellison’s Figure 1C, two DMA

3
Since we do not sustain the rejection of claims 17 and 18 as anticipated by
Houston, we do not sustain the rejection claims 7, 10 and 32 on the basis of
Houston and Tanenbaum.

Appeal 2010-000504
Application 09/943,242

14
peripherals in Zaidi’s Figure 28, and element 138 in Moriarty’s Figure 1,
each of which are accessible to a processor. Id. We further agree with the
Examiner’s finding that claim 32 merely requires that the first mass storage
device be coupled to the data/control bus and does not require a direct
coupling. Ans. 18-19. The Examiner further finds that Hunsaker’s CD ROM
172 and its controller 170 or any of the other PCI devices on the PCI buses
are coupled to the data/control bus (host bus 120) and are accessible to the
processor 110. Ans. 19. A Reply Brief was not filed in which the Examiner’s
findings with respect to claim 32 are disputed.
For all these reasons, we sustain the Examiner’s rejection of claim 32
as obvious over Hunsaker, Zaidi, or Moriarty in view of Tanenbaum.
4

Rejection of claim 22 as obvious over Hunsaker and Yiu
Appellant does not dispute the Examiner’s rejection of claim 22 as
obvious over Hunsaker and Yiu. Accordingly, we sustain the rejection of
claims 22 pro forma. See 37 C.F.R. § 41.37(c)(1)(vii).
DECISION
We AFFIRM the rejection of claims 1-3, 5 and 21 under 35 U.S.C.
§ 102(e) as anticipated by Hunsaker.
We AFFIRM the rejection of claims 1, 12 and 20 under 35 U.S.C.
§ 102(e) as anticipated by Zaidi.
We AFFIRM the rejection of claims 1 and 20 under 35 U.S.C.
§ 102(e) as anticipated by Moriarty.
We AFFIRM the rejection of claims 1 and 19 under 35 U.S.C.
§ 102(e) as anticipated by Ellison.

4
See footnote 2.

Appeal 2010-000504
Application 09/943,242

15
We REVERSE the rejection of claims 17 and 18 under 35 U.S.C.
§ 102(e) as anticipated by Houston.
We AFFIRM the rejection of claims 7, 10, and 32 under 35 U.S.C.
§ 103(a) as unpatentable over Hunsaker, Zaidi, or Moriarty in view of
Tanenbaum.
We AFFIRM the rejection of claim 22 under 35 U.S.C. § 103(a) as
unpatentable over Hunsaker and Yiu.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED-IN-PART

ELD