Ex Parte Lim et al

Patent Trial and Appeal Board

Oct 10, 2017

13541063 (P.T.A.B. Oct. 10, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/541,063 07/03/2012 Cheow Guan Lim 42792-0361 7174
38881 7590
Infineon Technologies AG
c/o Schiff Hardin LLP
666 Fifth Avenue
Suite 1700
NEW YORK, NY 10103
EXAMINER
DORMAN, CHRISTIAN M
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
10/12/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
lbrutman @ schiffhardin.com
patents-NY @ schiffhardin.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHEOW GUAN LIM and GIOVANNI FERRARA
Appeal 2017-002034
Application 13/541,0631
Technology Center 2100
Before THU A. DANG, KRISTEN L. DROESCH, and
CARL L. SILVERMAN, Administrative Patent Judges.
SILVERMAN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—6, 8—13, 15—19, and 21—25, which constitute all
the pending claims. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
STATEMENT OF THE CASE
Appellants’ invention relates to defect detection and localization in
1 The real party in interest is identified as Infineon Technologies Austria
AG. App. Br. 1.
Appeal 2017-002034
Application 13/541,063
semiconductor chips. Abstract; Spec. 1:10 to 2:5. Claim 1, set forth below,
is exemplary of the subject matter on appeal (emphasis added):
1. A semiconductor chip defect detection and localization system
comprising:
a plurality of registers spaced apart from one another and coupled
with one another by a signal line, wherein the plurality of registers and
the signal line are arranged in a plurality of layers of a semiconductor
chip; and
logic circuitry coupled to the plurality of registers and configured to
determine a presence and a location of a physical defect in at least one of
the plurality of layers in which the plurality of registers and signal line
are arranged based on whether a signal propagates along the signal line
and through one or more of the plurality of registers, wherein the logic
circuitry is configured to determine the location of the physical defect in
at least one of the plurality of layers based on a failure of a signal to
propagate from a first one of the plurality of registers along the signal
line to a second adjacent one of the plurality of registers, wherein the
location of the physical defect is proximate the first one or the second
adjacent one of the plurality of registers.
App. Br. 6 (Claims Appendix).
REJECTIONS
Claims 1—5, 8—13, 15—19, and 24—25 stand rejected under pre-AIA 35
U.S.C. § 103(a) as being unpatentable over Macnamee et al (WO
2008/093312 Al; pub. August 7, 2008) (“Macnamee”) in view of Takeoka
et al. (U.S. 2004/0195672 Al; pub. Oct. 7, 2004) (Takeoka”). Final Act. 4—
9.
Claim 6 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Macnamee, Takeoka, and Touba et al. (U.S 2011/0258501
Al; pub. Oct. 20, 2011) (“Touba”). Final Act. 9-10.
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Application 13/541,063
Claim 21 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Macnamee, Takeoka, and Abe et al. (U.S. 5,723,875; iss.
March 3, 1998) (“Abe”). Final Act. 10.
Claim 22 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Macnamee, Takeoka, and Takasuka et al. (U.S. Patent
2011/0113286 Al; pub. May 12, 2011) (“Takasuka”). Final Act. 10-11.
Claim 23 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Macnamee, Takeoka, and Katagi et al. Al (U.S.
2010/0293424 Al; pub. November 18, 2010) (“Katagi”). Final Act. 11-12.
ANALYSIS
Appellants argue Macnamee and Takeoka do not teach the claim 1
limitation wherein the plurality of registers and the signal line are arranged
in a plurality of layers of a semiconductor chip. App. Br. 4—5; Reply Br. 1—
2.
Appellants argue the Examiner admits Macnamee does not teach the
disputed limitation and, instead, the Examiner relies on Takeoka. App. Br 4
(citing Final Act 3, referring to Takeoka Fig. 9A, 1114). Appellants argue
the Examiner errs because Takeoka, Figure 9A, describes testing pads 51, 52
and “[a] pad ... is a conducting connection, whereas a register is a storage
unit.” Id. Appellants argue the Examiner then errs by referring to Takeoka,
Figure 3A, which illustrates flip flops 23 (registers). Id.
According to Appellants, the flip flops (registers) are not within a
semiconductor chip as required by the claim:
Figure 3 A, and related Figure 2, illustrate a silicon wiring substrate 20
having regions where chip IPs 21, 22 are mounted (indicated by broken
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Application 13/541,063
lines). Pieces of wiring 24 connect respective pads 25 of chip IPs 21,
22. Flip flops 23 are provided in the vicinity of and below end portions
of the pieces of wiring 24 located in regions where the chip IPs 21, 22
are mounted, and form a scan chain 30. The flip flops are not located
within a chip IP 21, 22, as required by the claims. Rather, the flip flops
23 are arranged in the silicon wiring substrate 20, on which the chip IPs
21, 22 are located. Takeoka therefore does not teach or suggest a
plurality of registers and a signal line arranged in a plurality of layers
of a semiconductor chip, as claimed.
App. Br. 4—5.
In the Reply Brief, Appellants contend Takeoka, Figure 9B, describes
“a chip IP-A, a chip IP-B, a chip IP-C, and a chip IP-D arranged on a silicon
wiring substrate 50 while being superposed one on another” and “[t]he
testing pad of the chip IP-A at the lowermost position is connected to a
wiring layer 55 in the silicon wiring substrate 50 via the plug 56.” Reply Br.
2. According to Appellants, the Examiner errs in finding “that each chip IP
is a different "layer" of a semiconductor chip, as claimed” because “[e]ach
chip IP is a different chip, and the chip IPs A-D are stacked on top of one
another.” Id. (citing Ans. 7). In particular, the claims require the multiple
layers be within a single chip, not a plurality of chips. Appellants further
argue the Examiner errs by “tak[ing] bits and pieces from separate
references” and applying hindsight. Id.
The Examiner finds Appellants improperly narrowly interpret the
disputed limitation to require a plurality of registers on a plurality of layers
and, separately, the signal line is also arranged on a plurality of layers. Ans.
5—6. According to the Examiner, the claim only require the registers on a
first layer as long as the signal line is arranged on at least one other second
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Application 13/541,063
layer. Id. We agree with the Examiner’s interpretation and note Appellants
present no persuasive argument this interpretation is unreasonable,
overbroad, or inconsistent with the Specification. Claim terms in a patent
application are given the broadest reasonable interpretation consistent with
the Specification, as understood by one of ordinary skill in the art. In re
Crish, 393 F.3d 1253, 1256 (Fed. Cir. 2004).
Applying this interpretation, the Examiner finds, and we agree,
Takeoka teaches the signal line that is used to test the circuit is “arranged in
a plurality of layers of a semiconductor chip as is claimed.” Ans. 7 (citing
Takeoka Fig. 9B; also referring to Final Act 5 which refers to Takeoka Fig.
9A). In particular, the Examiner finds Takeoka, Figure 9 A, teaches each
semiconductor chip includes multiple layers through which a signal line
passes. Final Act. 5 (citing Takeoka Fig. 9A; 1114):
Takeoka in an analogous art teaches wherein each of multiple
individual semiconductor chips has multiple scan-in and scan-out
terminals [paragraph 0042] that are arranged across multiple cross
sections of each chip [paragraph 0114, figure 9A shows an individual
cross section] wherein thereby the multiple cross sections comprise
different layers of the semiconductor chips.
Id.
We are not persuaded by Appellants’ argument that the Examiner errs
in finding Takeoka teaches flip flops (registers) outside of the semiconductor
chip. Instead, we agree with the Examiner’s finding that Macnamee teaches
this limitation. Ans. 8—9 (citing Final Act. 4 referring to Macnamee 3:21—
23, 14:5—7). The rejection is based on the combination of Macnamee and
Takeoka and Appellants argue only Takeoka. In re Keller, 642 F.2d 413,
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Application 13/541,063
426 (CCPA 1981) (“[0]ne cannot show non-obviousness by attacking
references individually where, as here, the rejections are based on
combinations of references” (citations omitted)); In re Merck & Co., Inc.,
800 F.2d 1091, 1097 (Fed. Cir. 1986). Nor are we persuaded by Appellants’
conclusory argument regarding hindsight.
As stated by the Supreme Court, the Examiner’s obviousness rejection
must be based on:
“[Sjome articulated reasoning with some rational
underpinning to support the legal conclusion of
obviousness” .... [Hjowever, the analysis need not seek
out precise teachings directed to the specific subject
matter of the challenged claim, for a court can take
account of the inferences and creative steps that a person
of ordinary skill in the art would employ.
KSRInt’l. Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (quoting In re
Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).
The Examiner’s findings are reasonable because the skilled artisan is
“a person of ordinary creativity, not an automaton” and would “be able to fit
the teachings of multiple patents together like pieces of a puzzle.” KSR, 550
U.S. at 420-21.
On this record, Appellants do not present sufficient or persuasive
evidence that the combination of the cited references was “uniquely
challenging or difficult for one of ordinary skill in the art” or “represented an
unobvious step over the prior art.” Leapfrog Enters., Inc. v. Fisher-Price,
Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 419-21).
In view of the above, we sustain the rejection of claim 1, and
independent claims 16 and 25 which recite the disputed limitation and are
argued together with claim 1. We also sustain the rejection of dependent
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claims 2—6, 8—13, 15, 17—19, and 21—24 as these claims are not argued
separately. See 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
We affirm the Examiner’s decision rejecting claims 1—6, 8—13, 15—19,
and 21—25.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED
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