Ex Parte Liao et al

Patent Trial and Appeal Board

Nov 26, 2014

11552135 (P.T.A.B. Nov. 26, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte CHUN-TING LIAO, AN-MING LEE,
JUN-JIE XIE, and YING-HUI ZHU
___________

Appeal 2012-007553
Application 11/552,135
Technology Center 2100
____________

Before JEAN R. HOMERE, DANIEL N. FISHMAN, and
CATHERINE SHIANG, Administrative Patent Judges.

FISHMAN, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) of the final rejection of
claims 1–4, 6–16, and 18–20. Claims 5 and 17 are cancelled.1 We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 In this Opinion, we refer to Appellants’ Appeal Brief (“App. Br.,” filed
October 13, 2011), Appellants’ Reply Brief (“Reply Br.,” filed April 12,
2012), the Examiner’s Answer (“Ans.,” mailed February 17, 2012), and the
originally filed Specification (“Spec.,” filed October 23, 2006).
Appeal 2012-007553
Application 11/552,135

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STATEMENT OF THE CASE
THE INVENTION
The invention relates to a Universal Serial Bus (USB) apparatus that
does not require an external accurate frequency oscillator to reduce the
manufacturing costs without affecting the product performance. Spec. ¶ 7.
Claim 1, reproduced below, is illustrative:
1. A Universal Serial Bus (USB) apparatus, comprising:
a signal detecting unit, for detecting a packet signal
transmitted from a USB host and generating an
acknowledgment signal in response to a detection result
indicating that the packet signal is a start of frame (SOF) packet
signal;
an error detecting unit, coupled to the signal detecting
unit, for utilizing an output clock signal to count a time interval
between two adjacent acknowledgment signals to generate a
counting result and generating a control signal according to the
counting result; and
a frequency generating unit, coupled to the error
detecting unit for generating the output clock signal according
to the control signal.

THE REJECTIONS
Claims 1, 6–12, 15, 16, 18, and 19 are rejected under 35 U.S.C.
§ 102(b) as anticipated by Leydier (US 2004/0148539 A1; July 29, 2004).
Claims 2–4, 13, 14, and 20 are rejected under 35 U.S. C. § 103(a) as
unpatentable over Leydier and USB Specification (Compaq et al., Universal
Serial Bus Specification, Rev. 2.0, 2000).
Only those arguments actually made by Appellants have been
considered in this Decision. Arguments that Appellants did not make in the
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Briefs have not been considered and are deemed to be waived. See
37 C.F.R. § 41.37(c)(1)(vii) (2010).
We have reviewed the Examiner’s rejections in light of Appellants’
arguments the Examiner erred. App. Br. 4–9; Reply Br. 1–3. We are
unpersuaded by Appellants’ contentions. We adopt as our own the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken and as set forth in the Examiner’s Answer in response to Appellants’
Appeal Brief (see Ans. 11–13). However, we highlight and address specific
arguments and findings for emphasis as follows.

ISSUE
Appellants’ arguments present the following dispositive issue: Has the
Examiner erred by finding Leydier teaches all limitations of claim 1?

SECTION 102 REJECTION
ANALYSIS
SIGNAL DETECTING UNIT
Regarding the recited signal detecting unit, Appellants argue Leydier
fails to teach the recited function of “generating an acknowledgment signal
in response to a detection result indicating that the packet signal is a start of
frame (SOF) packet signal.” App. Br. 5. Appellants further argue the
acknowledge tokens of Leydier’s paragraph 79 “are not sent ‘in response to
a detection result indicating that the packet signal is a start of frame
(SOF) packet signal.’” App. Br. 5–6. We are not persuaded the Examiner
erred.
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Application 11/552,135

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Initially, we note Appellants’ arguments suggest Leydier’s
acknowledge tokens are not sent responsive to detecting an SOF. However,
claim 1 only requires that the recited acknowledgment signal be generated in
response to detecting the SOF. Thus, Appellants’ arguments are not
commensurate with the scope of the claim.
Additionally, the Examiner does not rely solely on the acknowledge
tokens of Leydier. Rather, the Examiner finds, “for acknowledgment signal,
view CSOF signal 70 and any other usage made based on the SOFs as in
[0075] line 15, and/or acknowledgment tokens as shown in [0079].” Ans. 5.
Further, the Examiner explains Leydier teaches a general signal indicating
recognition of an SOF (in addition to an acknowledge token transmitted to
the sender of the SOF). Ans. 11. Specifically, the Examiner finds Leydier
teaches the acknowledgement signal as “CSOF signal 70 and any other
usage made based on the SOFs as in [0075] line 15, and/or
acknowledgement tokens shown in [0079].” Ans. 5 (citing Leydier ¶ 80).
We agree. In other words, Leydier teaches recognizing receipt of an SOF
and at least the CSOF signal is generated responsive to such recognition.
See Leydier Fig. 17, ¶ 80. The Examiner explains that this interpretation of
acknowledgement signal is consistent with Appellants’ Specification. Ans.
11 (quoting Spec. ¶ 27 “If the received signal is a SOF packet signal, an
acknowledgment signal is generated and passed to the next circuit.”); See
also Spec. ¶ 29. Contrary to Appellants’ response (Reply Br. 2–3), we find
the Examiner’s mapping of the recited acknowledgement signal to the
generation of the CSOF signal of Leydier is a broad but reasonable
interpretation and is consistent with the Specification.
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In view of the above discussion, we are not persuaded the Examiner
erred by finding Leydier teaches the signal detecting unit of claim 1.

Error Detecting Unit
Regarding the recited error detecting unit, Appellants argue Leydier
fails to teach the recited function, “utilizing an output clock signal to count a
time interval between two adjacent acknowledgment signals to generate a
counting result and generating a control signal according to the counting
result.” App. Br. 6–7. Specifically, Appellants quote paragraphs 75 and 79
of Leydier and conclude it can be “readily verified . . . Leydier fails to
disclose” the disputed limitation. App. Br. 6. We are not persuaded the
Examiner erred.
Initially, we note merely reciting language of the claims and asserting
the cited prior art reference does not teach the claim limitation is
insufficient. See 37 C.F.R. § 41.37(c)(1)(vii) (“A statement which merely
points out what a claim recites will not be considered an argument for
separate patentability of the claim.”); see also In re Lovin, 652 F.3d 1349,
1357 (Fed. Cir. 2011) (“[W]e hold that the Board reasonably interpreted
Rule 41.37 to require more substantive arguments in an appeal brief than a
mere recitation of the claim elements and a naked assertion that the
corresponding elements were not found in the prior art.”). Appellants’
argument fails to provide sufficient, persuasive argument or evidence
regarding the specific deficiency of the Examiner’s findings with respect to
the error detecting unit of claim 1. Regardless, the Examiner explains
Leydier paragraph 75 counts the number of bits received between receipt of
two consecutive SOFs. Ans. 12. We agree. As discussed supra, each
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received SOF generates (toggles) a CSOF signal (acknowledgement signal)
and thus counting bits between two consecutive SOFs teaches determining a
time interval between two acknowledgement signals (i.e., between two
CSOF signals).
Appellants further argue Leydier paragraph 79 fails to teach
generating a control signal according to a counting result. App. Br. 6–7.
We are not persuaded the Examiner erred. The Examiner further explains
Leydier uses any discrepancy between the actual count of bits between
CSOF signals and the expected count (e.g., 12000) to adjust its clock—such
a discrepancy used for adjustment teaches a control signal. Ans. 6, 12. We
agree. Leydier clearly teaches synthesizing a clock and adjusting the
synthesized clock based on the actual count of bits between consecutive
SOFs as compared to the expected count—i.e., a control signal (time interval
discrepancy) generated based on the counting result (i.e., time interval as
counted). See Ans. 13 (citing Leydier Fig. 6, element 270); see also Leydier
¶¶ 66–70; see also Leydier Fig. 17, ¶ 80, Fig. 19, ¶¶ 132–141.
In view of the above discussion, we are not persuaded the Examiner
erred by finding Leydier teaches the error detecting unit of claim 1.

Frequency Generating Unit
Regarding the recited frequency generating unit, Appellants argue
Leydier fails to teach the recited function “generating the output clock signal
according to the control signal.” App. Br. 8–9. Specifically, Appellants
argue element 395D of Leydier’s Figure 3 (read by the Examiner as the
recited frequency generating unit) does not perform the function of
generating the output clock according to the control signal (generated by the
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error detecting unit discussed supra). App. Br. 8; Reply Br. 1–2. We are
not persuaded the Examiner erred.
The Examiner explains element 395D of Leydier’s Figure 3 is the
clock synthesizer discussed in Leydier and paragraph 75 of Leydier teaches
the clock signal is synthesized based on the measured counts between
consecutive received SOFs. Ans. 13. We agree. As discussed supra,
Leydier determines a difference/discrepancy between the actual counted bits
between two acknowledgement signals (CSOF toggles) and the expected
number of bits. That difference (a control signal) is used to adjust the output
clock in a feedback loop. See Leydier Fig. 6, ¶¶ 66–70; see also Leydier
Fig. 19, ¶¶ 132–141.
In view of the above discussion, we are not persuaded the Examiner
erred by finding Leydier teaches the frequency generating unit of claim 1.

In view of the above discussion, we are not persuaded the Examiner
erred by finding Leydier teaches all limitations of independent claim 1.
Appellants argue the Examiner erred in rejecting independent claim 12 for
the same reasons as claim 1 (App. Br. 9) and thus, for the same reasons as
claim 1, we are not persuaded of error. Appellants do not separately argue
patentability of dependent claims 6–11, 15, 16, 18, and 19 (see App. Br. 9)
and thus, for the same reasons as claim 1, we are not persuaded of error and
we sustain the rejection of claims 1, 6–12, 15, 16, 18, and 19.

Appeal 2012-007553
Application 11/552,135

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SECTION 103 REJECTION
ANALYSIS
Appellants do not separately argue patentability for dependent claims
2–4, 13, 14, and 20 (App. Br. 9) and thus, for at least the same reasons as
claim 1, we are not persuaded the Examiner erred and we sustain the
rejection of claims 2–4, 13, 14, and 20 under § 103.

DECISION
For the above reasons, the Examiner’s decisions rejecting claims 1–4,
6–16, and 18–20 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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