Ex parte LESK et al.

Board of Patent Appeals and Interferences

May 20, 1998

07829660 (B.P.A.I. May. 20, 1998)

Application for patent filed February 3, 1992.1
1
THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered today
(1) was not written for publication in a law journal and
(2) is not binding precedent of the Board.
Paper No. 15
UNITED STATES PATENT AND TRADEMARK OFFICE
__________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________
Ex parte ISRAEL A. LESK, ROBERT B. DAVIES,
ROBERT E. RUTTER, and LOWELL E. CLARK
__________
Appeal No. 96-0155
Application 07/829,6601
__________
ON BRIEF
__________
Before GARRIS, WEIFFENBACH, and PAK, Administrative Patent
Judges.
GARRIS, Administrative Patent Judge.
DECISION ON APPEAL
Appeal No. 96-0155
Application No. 07/829,660
2
This is a decision on an appeal from the final rejection
of claims 1 through 25 which are all of the claims in the
application.
The subject matter on appeal relates to a method useful
in the backside processing of semiconductor wafers which
comprises bonding a processed first surface of the
semiconductor wafer to a support means such as a handle wafer
prior to processing a second surface of the wafer. This
appealed subject matter is adequately illustrated by
independent claims 8 and 18 which read as follows:
8. A method useful in the backside processing of
semiconductor wafers comprising the steps of:
providing a semiconductor wafer having a first surface
being substantially processed and a second surface;
bonding said first surface of said semiconductor wafer to
a handle wafer;
thinning said semiconductor wafer from said second
surface;
dicing said semiconductor wafer while bonded to said
handle wafer to form individual dice; and
removing said individual dice from said handle wafer.
18. A method useful in the backside processing of
semiconductor wafers comprising the steps of:
Appeal No. 96-0155
Application No. 07/829,660
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providing a semiconductor wafer having a first surface
being substantially processed and a second surface;
bonding said first surface of said semiconductor wafer to
support means;
thinning said semiconductor wafer from said second
surface;
implanting impurities into said semiconductor wafer
through said second surface; and
removing said semiconductor wafer from said support
means.
The prior art relied upon by the examiner as evidence of
obviousness is set forth below:
Corrie 4,946,716 Aug. 7, 1990
Admitted Prior Art Pages 1-2 of the specification
All of the claims on appeal stand rejected under the
first paragraph of 35 U.S.C. § 112 "as failing to provide an
adequate written description of the invention" (answer, page
3, also page 4).
Claims 8 through 14 and 18 through 25 stand rejected
under 35 U.S.C. § 103 as being unpatentable over the admitted
prior art in view of Corrie.
Although the appellants assert that at least certain of
the appealed claims should not stand or fall together (see
pages 4 and 5 of the brief), no specific arguments have been
Appeal No. 96-0155
Application No. 07/829,660
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advanced concerning any particular claim taken individually.
See 37 CFR § 1.192(c)(5)(6)(1993) and Ex parte Schier, 21
USPQ2d 1016, 1019 (Bd. Pat. App. & Int. 1991). As a
consequence, we will treat the claims as standing or falling
together in accordance with their groupings in the above noted
rejections.
OPINION
The section 112, first paragraph, rejection of appealed
claims 1 through 25, whether based on the written description
requirement or the enablement requirement, cannot be sustained
for the reasons well stated by the appellants on pages 5
through 7 of their brief.
Concerning the section 103 rejection, the appellants
contend that neither Corrie nor the admitted prior art
contains any teaching or suggestion of the bonding feature or
the handle wafer/support means feature of their rejected
claims and argue that "prior art which doos [sic, does] not
teach or suggest bonding, a handle wafer, nor a bonding
intermediate or binder can [sic, cannot] render obvious claims
specifically reciting bonding a surface of a semiconductor
wafer to either support means or a handle wafer" (brief, page
Appeal No. 96-0155
Application No. 07/829,660
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8). In response, the examiner explicitly points out, inter
alia, that "col. 2, lines 51-60 of Corrie teaches and suggests
as much" (answer, page 7).
The above noted portion of the Corrie reference refers to
a prior art patent in which "it is proposed that a CCD
imager... should be supported during thinning by means of a
plate of molybdenum, aluminum or glass that is bonded to the
die using epoxy adhesive or a bonding alloy" (col. 2, lines
51-56). Thus, as indicated by the examiner, the aforequoted
disclosure teaches bonding (i.e., via epoxy adhesive or a
bonding alloy) a wafer (i.e., a CCD imager) to a handle
wafer/support means (i.e., a plate of molybdenum, aluminum or
glass). Moreover, it is significant that the appellants have
not filed a reply brief or any other response challenging the
examiner's position on this matter.
In essence, the examiner has specifically identified the
portion of the Corrie reference which he considers to disclose
the here claimed features argued by the appellants to be not
taught or suggested by the prior art, and the examiner's
position on this matter has not been contested by the
appellants on the record before us. Under these
Appeal No. 96-0155
Application No. 07/829,660
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circumstances, we have little choice but to regard as
unpersuasive the appellants' arguments against the examiner's
section 103 rejection. We shall sustain, therefore, the
rejection of claims 8 through 14 and 18 through 25 under 35
U.S.C. § 103 as being unpatentable over the admitted prior art
in view of Corrie.
The decision of the examiner is affirmed-in-part.
No time period for taking any subsequent action in
connection with this appeal may be extended under
37 CFR § 1.136(a).

AFFIRMED-IN-PART
Appeal No. 96-0155
Application No. 07/829,660
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Bradley R. Garris )
Administrative Patent Judge )
)
)
)
Cameron Weiffenbach ) BOARD OF
PATENT
Administrative Patent Judge ) APPEALS AND
) INTERFERENCES
)
)
Chung K. Pak )
Administrative Patent Judge )
Appeal No. 96-0155
Application No. 07/829,660
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Vincent J. Rauner
Motorola, Inc.
Intellectual Property Department
P.O. Box 10219
Scottsdale, Arizona 85271-0219