Ex Parte Legakis et alDownload PDFPatent Trial and Appeal BoardJun 20, 201612240382 (P.T.A.B. Jun. 20, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/240,382 09/29/2008 102324 7590 06/22/2016 Artegis Law Group, LLP/NVIDIA 7710 Cherry Park Drive Suite T #104 Houston, TX 77095 FIRST NAMED INVENTOR Justin S. Legakis UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. NVDA/SC-08-0251-US 1 5276 EXAMINER NGUYEN, ANH TUAN V ART UNIT PAPER NUMBER 2614 NOTIFICATION DATE DELIVERY MODE 06/22/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): kcruz@artegislaw.com ALGdocketing@artegislaw.com mmccauley@artegislaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JUSTIN S. LEGAKIS, EMMETT M. KIGARIFF, and HENRY PACKARD MORETON Appeal2013-010154 Application 12/240,382 Technology Center 2600 Before JOHN A. JEFFERY, BRADLEY W. BAUMEISTER, and DENISE M. POTHIER, Administrative Patent Judges. BAUMEISTER, Administrative Patent Judge. DECISION ON APPEAL Appeal2013-010154 Application 12/240,382 SUMMARY Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's rejection of claims 1, 4--8, 11-17, 21, and 23 (Ans. 3-10): 1 These claims presumably stand rejected under 35 U.S.C. § 112, i-f 2, as indefinite. App. Br. 7. These claims also stand rejected under 35 U.S.C. § 103(a) as obvious over the combination of the following four references: (i) Wei et al. (US 2009/0237401 Al; published Sept. 24, 2009); (ii) Ujval J. Kapasi et al., The Image Stream Processor, (1-7) PROCEEDINGS OF THE 2002 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS ("Kapasi"); and (iii) Jiao (US 2009/0251476 Al; published Oct. 8, 2009). 2 Ans. 3-10, 14; see also Adv. Act. We have jurisdiction under 35 U.S.C. § 6(b). We review the appealed rejection for error based upon the issues identified by Appellants, and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). We affirm. 1 Rather than repeat the Examiner's positions and Appellant's arguments in their entirety, we refer to the following documents for their respective details: the Final Action mailed October 30, 2012 ("Final Act."); the Advisory Action mailed January 9, 2013 ("Adv. Act."); the Appeal Brief filed April 1, 2013, as amended by the Response to Notification ofNon- Compliant Appeal Brief Under 37 C.F.R. § 41.37 filed May 2, 2013 ("App. Br."); the Examiner's Answer mailed June 13, 2013 ("Ans."); and the Reply Brief filed August 13, 2013 ("Reply Br."). 2 In order to provide evidence of an inherent characteristic of Jiao' s index buffers, the Examiner further cites Index buffers (Direct3D 9) ("Index buffers"), available at http://msdn.microsoft.com/en- us/library/windows/desktop/bbl 74595(v=vs.85).aspx. Ans. 14. 2 Appeal2013-010154 Application 12/240,382 STATEMENT OF CASE Appellants describe the present invention as follows: A system and method for performing tessellation in a single pass through a graphics processor divides the processing resources within the graphics processor into sets for performing different tessellation operations. Vertex data and tessellation parameters are routed directly from one processing resource to another instead of being stored in memory. Therefore, a surface patch description is provided to the graphics processor and tessellation is completed in a single uninterrupted pass through the graphics processor without storing intermediate data in memory. (Abstract). Independent claim 1, reproduced below with our emphasis, is illustrative of the appealed claims: 1. A method for performing tessellation in a single pass through a graphics processor, the method comprising: configuring a first set of processing units of the graphics processor to execute a tessellation control shader to process surface patches and produce a graphics primitive including multiple vertices; configuring a second set of the processing units within the graphics processor to execute a tessellation evaluation shader to each process one of the multiple vertices, wherein each of the processing units in the first set and in the second set is a streaming multiprocessor unit including an identical set of functional units; executing the tessellation control shader and the tessellation evaluation shader to tessellate the surface patches in a single pass through the first set of processing units and the second set of processing units to produce processed vertices; writing the multiple vertices to a cache by the first set of the processing units; and 3 Appeal2013-010154 Application 12/240,382 reading the multiple vertices from the cache by the second set of the processing units, wherein the multiple vertices are not stored in graphics memory; distributing the multiple vertices output by the first set of the processing units to inputs of the second set of the processing units, wherein the step of distributing comprises routing indices corresponding to a location storing each of the multiple vertices from the first set of the processing units to inputs of the second set of the processing units. THE INDEFINITENESS REJECTION Ambiguity exists as to whether the pending claims stand rejected under 35 U.S.C. § 112, i-f 2, as being indefinite. Then-pending claims 1-8, 11-17, 20, 21, and 23 initially were so rejected as being indefinite. Final Act. 2. Appellants subsequently filed a proposed claim amendment in their Response to Office Action Dated October 30, 2012 (filed Dec. 31, 2012) ("After-Final Response"), amending independent claims 1 and 11 in a manner unrelated to the allegedly indefinite claim language, as well as additionally cancelling claims 2, 3, and 20. The Examiner entered this amendment, but did not explain on the record whether this amendment addressed the indefiniteness rejection, or whether the indefiniteness rejection was being maintained. See Adv. Act. On Appeal, Appellants acknowledge that the claims were rejected as indefinite. App. Br. 7. But Appellants then do not present any arguments regarding the indefiniteness rejection (see id. 7-9). The Examiner, though, does not address the indefiniteness rejection expressly in the Answer either. See generally Ans. More specifically, the Answer initially states in the GROUNDS OF REJECTION TO BE REVIEWED ON APPEAL section, that 4 Appeal2013-010154 Application 12/240,382 [t]he examiner has no comment on [Appellants'] statement of the grounds of rejection to be reviewed on appeal. Every ground of rejection set forth in the Office action from which the appeal is taken. . . is being maintained by the examiner except for the grounds of rejection (if any) listed under the subheading "WITHDRAWN REJECTIONS." New grounds of rejection (if any) are provided under the subheading "NEW GROUNDS OF REJECTION." Ans. 3. The GROUNDS OF REJECTION TO BE REVIEWED ON APPEAL section then only sets forth the obviousness rejection, omitting any mention of the indefiniteness rejection. Ans. 3-10. This is so even though the Answer does not include any section with the subheading "WITHDRAWN REJECTIONS," or otherwise expressly indicate that the indefiniteness rejection was withdrawn. See generally Ans. Therefore, it is unclear whether the Examiner intended to withdraw the indefiniteness rejection. What is clear, though, is that Appellants acknowledge that the indefiniteness rejection is pending (App. Br. 7; Reply Br. 5), and Appellants do not present any substantive arguments in relation to the indefiniteness rejection (App. Br. 7-8; Reply Br. 5-8. Accordingly, we accept Appellants' statements in their Briefs as an admission that the indefiniteness rejection is pending. We view Appellants' subsequent silence on the issue as a failure to respond to a pending rejection. Accordingly, we summarily sustain the indefiniteness rejection of claims 1, 4--8, 11-17, 21, and 23 under 35 U.S.C. § 112, i-f 2. See MPEP § 1205.02, ("If a ground of rejection stated by the examiner is not addressed in the appellant's brief, that ground of rejection will be summarily sustained by the Board."). 5 Appeal2013-010154 Application 12/240,382 THE OBVIOUSNESS REJECTION Arguments The Examiner finds that Wei discloses a method for performing tessellation in a single pass through a graphics processor that includes most of the limitations of independent claim 1, but does not teach that each of the processing units in the first and second sets is a streaming multiprocessor unit including an identical set of functional units. Ans. 3-5. The Examiner relies on Kapasi for teaching this claim limitation. Ans. 5. The Examiner further finds that while "Wei teaches distributing the multiple vertices output by the first set of the processing units to inputs of the second set of the processing units," Wei does not teach the emphasized language of claim 1, as reproduced in the Opinion above. Ans. 6. That is, the Examiner finds that Wei does not expressly teach "wherein the step of distributing comprises routing indices corresponding to a location storing each of the multiple vertices from the first set of the processing units to inputs of the second set of the processing units." The Examiner finds, though, that Jiao teaches this missing limitation. Ans. 6 (citing Jiao i-f 32); id. 14 (citing Jiao i-fi-132, 35). The Examiner further sets forth alleged motivation for incorporating the teachings of Kapasi and Jiao into Wei. Id. The Examiner additionally explains in the Answer's RESPONSE TO ARGUMENT section that the Index Buffers web page is cited to show inherent features of Jiao's index buffers. Ans. 14. Specifically, the Examiner concludes that the term "[i]ndex buffer" is a term of art meaning "a buffer having indices that are 'integer offsets into vertex buffers."' Id. 6 Appeal2013-010154 Application 12/240,382 Appellants do not dispute whether an index buffer inherently contains indices. App. Br. 8. Appellants instead argue that even if the Examiner's conclusion regarding inherency is true, Id. Jiao [merely] describes an input assembler utilizing index buffers to fetch vertex data from the memory so that the assembler can assemble primitives, but fails to describe routing the indices "corresponding to a location storing each of the multiple vertices from the first set of the processing units to inputs of the second set of the processing units" as recited in claim 1. Analysis The portions of Jiao relied upon by the Examiner-paragraphs 32 and 35 and Figure 4-----do teach, e.g., that "[t]he command stream processor 406 provides triangle vertex indices to the [execution unit ('EU')] pool control unit 206." Jiao i-f 35. However, these passages do not support the Examiner's further conclusion that Jiao teaches routing indices from the first processing unit to inputs of the second processing unit. See Ans. 6. Rather, Jiao merely describes the function of the EU pool control unit 206 as follows: The EU pool control unit 206 assembles vertex shader inputs from the stream cache and sends data to the computational core 204 (input E). The EU pool control unit 206 also assembles geometry shader inputs and provides those inputs to the computational core 204 (input F). In general, the EU pool control unit 206 controls the respective inflow and outflow to the computational core 204. Jiao i-f 35. Nor does paragraph 32 of Jiao further address the type of vertex data transferred between processors. Jiao i-f 32. This level of explanation does not reasonably demonstrate Jiao teaches the disputed claim language. Accordingly, the Examiner has not 7 Appeal2013-010154 Application 12/240,382 established that the cited prior art teaches the disputed limitation, so we are persuaded us of error in the Examiner's obviousness rejection of independent claim 1. We are likewise persuaded of error in the obviousness rejection of independent claim 11, which sets forth similar language. We therefore will not sustain the Examiner's obviousness rejection of those claims or of claims 4--8, 12-1 7, 21, and 23, which depend from claims 1 or 11. CONCLUSIONS We summarily sustain the indefiniteness rejection of claims 1, 4--8, 11-17, 21, and 23 under 35 U.S.C. § 112, i12. We do not sustain the obviousness rejection of claims 1, 4--8, 11-17, 21, and 23 under 35 U.S.C. § 103. DECISION The Examiner's decision rejecting claims 1, 4--8, 11-17, 21, and 23 is affirmed. AFFIRMED 8 Copy with citationCopy as parenthetical citation