Ex Parte LeedyDownload PDFPatent Trial and Appeal BoardJun 19, 201814032844 (P.T.A.B. Jun. 19, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. 14/032,844 30232 7590 USEFUL ARTS IP MICHAEL J. URE 1501 E. Spring Lane Holladay, UT 84117 FILING DATE FIRST NAMED INVENTOR 09/20/2013 Glenn J. Leedy 06/21/2018 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 130920VSI.US 7947 EXAMINER LUKE, DANIEL M ART UNIT PAPER NUMBER 2813 NOTIFICATION DATE DELIVERY MODE 06/21/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): mureakasolo@gmail.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Exparte GLENN J. LEEDY Appeal2017-008532 Application 14/032,844 1 Technology Center 2800 Before DONNA M. PRAISS, BRIAND. RANGE, and SHELDON M. McGEE, Administrative Patent Judges. RANGE, Administrative Patent Judge. DECISION ON APPEAL SUMMARY Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's decision rejecting claims 13-25. We have jurisdiction. 35 U.S.C. § 6(b ). We AFFIRM. 1 According to Appellant, the real party in interest is Glenn J. Leedy. Appeal Br. 3. Appeal2017-008532 Application 14/032,844 STATEMENT OF THE CASE2 Appellant describes the invention as relating to a Vertical System Integration ("VSI") apparatus that provides a stack of closely coupled component (die or integrated circuit ("IC")) layers. Spec. 1. Claim 13, reproduced below with formatting added for readability, is the only independent claim on appeal and is illustrative of the claimed subject matter: 13. A stacked integrated circuit that is one of a family of stacked integrated circuits formed from a library of integrated circuit layers designed to be stacked as part of a stacked integrated circuit, comprising a plurality of closely-coupled integrated circuit layers selected from the library and stacked in relation to one another, and a plurality of vertical interconnections in a standardized placement interconnecting at least two of the plurality of closely-coupled integrated circuit layers. Appeal Br. 16 (Claims App.). REFERENCES The Examiner relies upon the prior art below in rejecting the claims on appeal: Leedy Takemoto us 5,915,167 US 2002/0017610 Al REJECTIONS June 22, 1999 Feb. 14,2002 The Examiner maintains the following rejections on appeal (Ans. 2): 2 In this Decision, we refer to the Final Office Action dated December 10, 2015 ("Final Act."), the Appeal Brief filed July 26, 2016 ("Appeal Br."), and the Examiner's Answer dated January 13, 2017 ("Ans."). 2 Appeal2017-008532 Application 14/032,844 Rejection 1. Claims 20-25 under 35 U.S.C. § 112 as failing to comply with the written description requirement. Final Act. 2-3. Rejection 2. Claim 14 under 35 U.S.C. § 112 as indefinite. Id. at 3. 3 Rejection 3. Claims 13-16 and 19 under 35 U.S.C. § 102 as anticipated by Leedy. Id. at 4--5. Rejection 4. Claims 17 and 18 under 35 U.S.C. § 103 as unpatentable over Leedy in view of Takemoto. Id. at 5. ANALYSIS We review the appealed rejections for error based upon the issues identified by Appellant and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential), cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) ("[I]t has long been the Board's practice to require an applicant to identify the alleged error in the examiner's rejections."). After considering the evidence presented in this Appeal and each of Appellant's arguments, we are not persuaded that Appellant identifies reversible error. Thus, we affirm the Examiner's rejections for the reasons expressed in the Final Office Action and the Answer. We add the following primarily for emphasis. Rejection 1. The Examiner rejects claims 20-25 under 35 U.S.C. § 112 as failing to comply with the written description requirement. Final Act. 2-3. Appellant argues claims 20-25 as a group, and we therefore focus on claim 20. 37 C.F.R. § 4I.37(c)(l)(iv) (2013). Claims 21-25 stand or fall together with claim 20. Claim 20 is reproduced below: 3 As further explained below, the Final Office Action mistakenly refers to claim 13 rather than claim 14 for this rejection. 3 Appeal2017-008532 Application 14/032,844 20. The stacked integrated circuit of claim 13, wherein integrated circuit layers identical to said at least two of the closely-coupled integrated circuit layers are used in one or more stacked integrated circuits, wherein the one or more stacked integrated circuits do not comprise integrated circuit layers identical to all of the integrated circuit layers of the stacked integrated circuit. Appeal Br. 17 (Claims App.). The Examiner finds that the Specification does not support integrated circuit layers having the relationship recited by claim 20. Final Act. 2-3; Ans. 6-8. Pursuant to the written description requirement of 35 U.S.C. § 112, the disclosure of the application relied upon must "reasonably convey[] to those skilled in the art that the inventor had possession of the claimed subject matter as of the filing date." Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en bane). The written description inquiry is a question of fact. Id. Here, Appellant argues that three teachings from the Specification support the recitations of claim 20. Appeal Br. 12-13. First, Appellant argues that the Specification at Figure 26A and page 177, first full paragraph, teaches that "the memory layers of a stacked integrated circuit can be the same but the FPGA logic layers can be different." Id. at 12. Upon review of these passages, however, we concur with the Examiner's finding that these portions of the Specification do not compare with another stacked integrated circuit or one having the same memory layers but different FPGA logic layers. Ans. 7. 4 4 The Examiner's findings in the Answer are undisputed because Appellant did not file a Reply Brief. 4 Appeal2017-008532 Application 14/032,844 Second, Appellant argues that Figure 27 A and page 178, line 9, to page 179, line 11 teach that network processor (NP) circuit layers may vary and the rest of the stack, such as memory and I/0 (input/output), remain the same. Appeal Br. 12. Upon review, we again concur with the Examiner's finding that the passage does not support Appellant's argument. Ans. 7. Third, Appellant argues that page 24 teaches a portion of stacked IC (integrated circuit) in common with other stacked ICs while another portion of stacked IC is different, such as the logic portion. Appeal Br. 12. Appellant appears to have intended to refer to page 7 4 of the Specification because it is page 7 4 that is entitled "First Preferred VSI embodiment" as referenced in the Appeal Brief. Ans. 7. In any event, we again concur with the Examiner that the cited passage ( whether looking at page 24 or page 7 4) does not appear to reference, for example, "a portion of a stacked IC is in common with a number of other stacked ICs." Id. For each of the Specification's teachings addressed above, Appellant's argument does not sufficiently direct us to, or explain language in the Specification that would tend to establish that, the Specification would have reasonably conveyed to those skilled in the art that the inventor had possession of the claimed subject matter as of the filing date. We therefore sustain the Examiner's rejection because Appellant has not identified reversible error. Rejection 2. The Examiner rejects claim 14 under 35 U.S.C. § 112 as failing to comply with the written description requirement. Final Act. 3. The Final Office Action identifies claim 13 in the statement of this rejection, but the Examiner corrects the typographical error in the Answer. Ans. 2. This error is harmless because the rejection was reasonably clear from the 5 Appeal2017-008532 Application 14/032,844 original rejection which quotes language that appears only in claim 14 and because of the Examiner's correction in the Answer. See Final Act. 3; Ans. 2. The Examiner maintains that the recitation "of different design" as recited in claim 14 is unclear. Final Act. 3; Ans. 2. Appellant does not respond. Because Appellant does not identify reversible error, we sustain this rejection. Jung, 637 F.3d at 1365. Rejection 3. The Examiner rejects claims 13-16 and 19 under 35 U.S.C. § 102 as anticipated by Leedy. Final Act. 4. Appellant does not separately argue claims 14--16 or 19. We therefore limit our discussion to claim 13. Claims 14--16 and 19 stand or fall with that claim. 3 7 C.F.R. § 4I.37(c)(l)(iv) (2013). Claim 13 is written in a product-by-process format because the recited "stacked integrated circuit" is defined "at least in part in terms of the method or process by which it is made." SmithKline Beecham Corp. v. Apotex Corp., 439 F.3d 1312, 1315 (Fed. Cir. 2006) (internal quotes and citation omitted). In particular, claim 13 defines the stacked integrated circuit as being "one of a family of stacked integrated circuits formed from a library of integrated circuit layers designed to be stacked as part of a stacked integrated circuit," recites that the layers are "selected from the library," and recites that the interconnections are "in a standardized placement." Consistent with the Specification, "standardized placement" refers to placement of interconnections being the same for different layers so that different layers can, when manufacturing another stacked integrated circuit, be coupled in different ways. See, e.g., Spec. 31 ("interconnections can be organized into standardized placements in the layouts of a family or library 6 Appeal2017-008532 Application 14/032,844 of circuit layers with the objective of enabling the subsequent direct coupling"). As Appellant puts it, "[ s ]tandardized placement makes possible the mix-and-match ... of selected stacked integrated circuit layers selected from the library." Appeal Br. 11. Because claim 13 is directed to a product, i.e. "[a] stacked integrated circuit," "determination of patentability is based on the product itself," not on "its method of production." In re Thorpe, 777 F.2d 695, 697 (Fed. Cir. 1985). "If the product in a product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." Id. "When the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable." In re Fessmann, 489 F.2d 742, 744 (CCPA 1974) (quote and citation omitted). Once the Examiner establishes a prima facie case of anticipation or obviousness, the burden "to prove that the prior art products do not necessarily or inherently possess the characteristics of his claimed product" shifts to the Appellant. Thorpe, 777 F.2d at 698 (citation omitted). Here, the Examiner finds that Leedy teaches each of the structural recitations of claim 13. Final Act. 4 (providing citations to Leedy). The Examiner presents ample evidence to establish that the stacked integrated circuit of Leedy is identical (or, alternatively, only slightly different than) the stacked integrated circuit of claim 1. Accordingly, the Examiner has set forth a prima facie case of anticipation that is supported by a preponderance of the evidence. 7 Appeal2017-008532 Application 14/032,844 Appellant argues that Leedy does not teach a library of layers, selecting layers from the library, or standardized placement. Appeal Br. 9-- 10. Each of these arguments is based on how the stacked integrated circuit is made rather than being based on structure. Appellant does not present any persuasive argument as to why the physical structure of the Leedy's stacked integrated circuit differs from the physical structure of the stacked integrated circuit of claim 13. As such, Appellant's argument does not establish reversible error. Moreover, in the alternative, the Examiner makes findings establishing how Leedy teaches each of the process recitations argued by Appellant. Ans. 2-6. Appellant does not persuasively dispute these findings or identify error in these findings. For the reasons above, we sustain this rejection. Rejection 4. The Examiner rejects claims 17 and 18 under 35 U.S.C. § 103 as unpatentable over Leedy in view of Takemoto. Final Act. 5. Appellant relies on the arguments presented with respect to Rejection 3 above. Appeal Br. 11. We sustain this rejection because those arguments do not identify reversible error. DECISION For the above reasons, we affirm the Examiner's rejections of claims 13-25. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED 8 Copy with citationCopy as parenthetical citation