Ex Parte Lee et al

Patent Trial and Appeal Board

Sep 25, 2018

14445035 (P.T.A.B. Sep. 25, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/445,035 07/28/2014
79141 7590 09/27/2018
Morgan Lewis Bockius LLP / Jamie Zheng Ph.D.
1400 Page Mill Road
Palo Alto, CA 94304
FIRST NAMED INVENTOR
Hyun Lee
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
129980-5073US 9700
EXAMINER
AHMED, ZUBAIR
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
09/27/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
padocketingdepartment@morganlewis.com
vskliba@morganlewis.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HYUN LEE and JA YESH R. BHAKTA
Appeal2018-000326
Application 14/445,035
Technology Center 2100
Before JOSEPH L. DIXON, JOYCE CRAIG, and SCOTT E. BAIN,
Administrative Patent Judges.
BAIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 2-25, which constitute all claims pending in the
application. Claim 1 has been canceled. We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.
1 Appellants identify Netlist, Inc. as the real party in interest. App. Br. 4.
Appeal2018-000326
Application 14/445,035
STATEMENT OF THE CASE
The Claimed Invention
Appellants' invention relates to a memory module including a
"module control device" and distributed data buffers. Abstract; Spec.
,r,r 2-3. The data buffers "regenerate a clock signal received from the
module control device and [] provide regenerated clock signals to respective
groups of memory devices." Abstract. This helps ensure "proper timing" of
control and/or data signals in a memory circuit, particularly as operating
speed and memory density increase. Spec. ,r 8.
Claims 2, 9, and 18 are independent. Claim 2 is illustrative of the
invention and the subject matter of the appeal, and reads as follows:
2. A memory module operable in a system with a memory
controller, the system operating according to a system clock, the
memory module having a data width of (N x n) bits, where N and
n are integers larger than one, comprising:
N data buffers each having a data width of n-bits and each
generating a respective local clock signal;
memory devices including a plurality of groups of
memory devices, each respective group of memory devices
communicating data with the memory controller via a respective
one of the N data buffers, the each respective group of memory
devices receiving and transmitting data signals in accordance
with the local clock signal generated by the respective one of the
data buffers; and
a module control device to receive command/address
(Cl A) signals and a system clock from the memory controller and
to output module CIA signals, data buffer control signals and a
module clock signal, the module clock signal being derived from
the system clock signal, the module control device transmitting
the module Cl A signals to at least some of the memory devices,
the module control device transmitting the data buffer control
signals and the module clock signal to the data buffers;
2
Appeal2018-000326
Application 14/445,035
wherein the module control device does not transmit any
clock signal to the memory devices; and
wherein each of the N data buffers generates the respective
local clock signal from the module clock signal received from
the module control device.
App. Br. 15 (emphases added).
The Re} ections on Appeal
Claims 2-5, 7, 9, 11-14, 16, 18-22, 24, and 25 stand rejected under
35 U.S.C. § I03(a) as unpatentable over Matsui (US 2004/0105292 Al; June
3, 2004) and Sutardja et al. (US 2007/0168781 Al; July 19, 2007)
("Sutardja"). Final Act. 7-18.
Claims 6, 10, and 15 stand rejected under 35 U.S.C. § I03(a) as
unpatentable over Matsui, Sutardja, and Carpenter et al. (US 2009/0116312
Al; May 7, 2009) ("Carpenter"). Final Act. 18-20.
Claims 8 and 17 stand rejected under 35 U.S.C. § I03(a) as
unpatentable over Matsui, Sutardja, and Sung et al. (US 2011/0110168 Al;
May 12, 2011) ("Sung"). Final Act. 20-21.
Claim 23 stands rejected under 35 U.S.C. § I03(a) as unpatentable
over Matsui, Sutardja, and Chu et al. (US 2008/0291758 Al; Nov. 27, 2008)
("Chu"). Final Act. 21-22.
ANALYSIS
We have reviewed the Examiner's rejections in light of the arguments
raised in the briefs, on the record before us. For the reasons set forth below,
we do not sustain the Examiner's rejections.
Appellants argue the Examiner erred in finding Matsui and Sutardja
teach or suggest a memory control module that "output[ s] the data buffer
3
Appeal2018-000326
Application 14/445,035
control signals as well as the module Cl A signals and module clock signal,"
as recited in independent claim 2. 2 App. Br. 9-10; Reply Br. 4--5.
Appellants contend the Examiner acknowledges Matsui "does not teach the
module control device," and that combining Matsui with Sutardja does not
cure the deficiencies of Matsui because the Examiner still does not identify
how the combination would "possibly transmit the [ required] Cl A signals to
at least some of the memory devices" recited in claim 2. App. Br. 10.
Appellants also argue that a person of ordinary skill in the art would have no
rationale or motivation for combining Matsui with Sutardja, that doing so
would render Matsui inoperable for its intended purpose, and that Matsui
teaches away from the proposed combination. App. Br. 10-12; Reply Br. 4--
6. Appellants assert that the Examiner must have relied on hindsight in
combining the references. App. Br. 11-12. Because we are persuaded, on
this record, that the Examiner has not articulated a sufficient rationale for
combining the references, we are persuaded of error.
In rejecting claim 2, the Examiner concedes that the "memory
system" described in Matsui does not include a "module control device"
which "receiv[es] command/address (C/A) signals and a system clock from
the memory controller" and "output[ s] module Cl A signals, data buffer
control signals and a module clock signal" in the manner recited in claim 2.
Ans. 9-10. The Examiner, however, finds these elements in the combination
of Sutardja' s "memory control module" with Matsui' s memory system. Id.
at 10-12. The Examiner finds it "would have been obvious to a person of
ordinary skill in the art" to "modify the scope of the invention of Matsui"
2 Independent claims 9 and 18 have limitations commensurate in scope with
claim 2. See infra at 6.
4
Appeal2018-000326
Application 14/445,035
with Sutardja's memory control module, including a clock generator
module." Id. at 11. The "motivation," the Examiner finds, "would be that
the buffer modules may include a phase locked loop (PLL) to generate local
phase-adjusted clock signals [citing Sutardja paragraph 136]." Id. The
Examiner further explains in the Answer that "Sutardja advocates [for] use
of a PLL [] in the buffer module [] for local clock synchronization and clock
frequency multiplication[,] whereas Matsui uses a DLL (delay-locked loop)
in buffers [] for the same purpose." Ans. 10-11. The Examiner explains
that "PLL offers advantages over a DLL as widely known in the art." Id. at
11. Thus, the Examiner finds, incorporating Sutardja's memory control
module in Matsui would "improve upon" Matsui. Id.
As Appellants argue, however, the Examiner's explanation for
combining the references is "confusing" at best. App. Br. 11. The memory
control module described in Sutardja is a "controller" that "generates"
command and address signals, not receives them from another controller
(i.e., the one in Matsui) as in the Examiner's proposed combination. Reply
Br. 4--5. Similarly, the clock generator in Sutardja, which the Examiner
cites as teaching part of the "module control device" recited in claim 2,
generates clock signals, whereas combining this element with Matsui in the
manner explained by the Examiner would result in the element receiving
clock signals from Matsui's memory controller. Id. at 5.
Moreover, the Examiner does not explain how finding "notable
differences between" the buffer module in Sutardja and the memory module
buffers in Matsui supports, rather than teaches away from, the proposed
combination. Ans. 10-11; In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994)
(reference teaches away from combination "when a person of ordinary skill,
5
Appeal2018-000326
Application 14/445,035
upon reading the reference ... would be discouraged from following the
path set out in the reference"). If the Examiner relied on some other
explanation for combining the references, it is not apparent in the record
before us.
Accordingly, on this record, we find the Examiner has not sufficiently
"articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness." KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,
418 (2007). Specifically, the Examiner has not rationally explained why one
of ordinary skill would be led to apply Sutardja's teachings regarding a
memory control module and clock generator, to Matsui's memory system
which already has a memory controller. See KSR Int 'l Co. v. Teleflex Inc.,
550 U.S. 398, 418 (2007).
For the foregoing reasons, we do not sustain the Examiner's rejection
of independent claim 2 as unpatentable over Matsui and Sutardja. For the
same reasons, we also do not sustain the same rejection of independent
claims 9 and 18, which include limitations commensurate in scope with
claim 2. We also do not sustain the rejections of the remaining dependent
claims, each of which relies (in whole or in part) on the Matsui-Sutardja
combination.
DECISION
The Examiner's decision rejecting claims 2-25 is reversed.
REVERSED
6