Ex Parte Lee et al

Patent Trial and Appeal Board

Jul 31, 2013

10403863 (P.T.A.B. Jul. 31, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte RUBY B. LEE and DALE MORRIS
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Appeal 2011-001451
Application 10/403,8631
Technology Center 2100
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Before THU A. DANG, JAMES R. HUGHES, and
JEFFREY S. SMITH, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed March 31, 2003. The real party in interest is Hewlett-
Packard Co. (App. Br. 3.)
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2

STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134 of the Examiner’s
final decision rejecting claims 15-24, which are all the claims remaining in
the application. Claims 1-14 and 25-28 have been canceled. (App. Br. 5.)2
The Examiner has indicated claims 17 and 22 contain allowable subject
matter. (App. Br. 5; Ans. 2; Fin. Rej. 10.) We have jurisdiction under 35
U.S.C. § 6(b).
We affirm.
Appellants’ Invention
The invention at issue on appeal concerns a computer-readable
storage medium and data processor including an execution unit for executing
a tree-add instruction that provides a particular sum as the result. (Spec. ¶¶
[2], [16]-[22]; Abstract.)
Representative Claim
Independent claim 15, reproduced below, with disputed limitations
italicized, further illustrates the invention:
15. A data processor comprising:
n-bit registers including a first operand register and a
result register; and
a hardware execution unit for executing a tree-add
instruction so as to write an n-bit result in said result register,
said n-bit result having a magnitude equal to a magnitude of a
sum of at least p addends, p of said addends having magnitudes
equal to magnitudes of p q-bit operands stored in said first

2 We refer to Appellants’ Specification (“Spec.”); Appeal Brief (“App. Br.”)
filed May 14, 2010; and Reply Brief (“Reply Br.”) filed October 11, 2010.
We also refer to the Examiner’s Answer (“Ans.”) mailed August 16, 2010.
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operand register, where n, p, and q are counting numbers, p ≥ 4,
and p*q = n, said tree-add instruction specifying said first
operand register.
Rejections on Appeal
1. The Examiner rejects claims 15 and 20 under 35 U.S.C.
§ 102(b) as being anticipated Freescale Semiconductor, AltiVec Technology
Programming Interface Manual, (June 1999) (“AltiVec”).
3. The Examiner rejects claims 15, 16, 18-21, 23, and 24 under 35
U.S.C. § 103(a) as being unpatentable over U.S. Patent No. 6,243,803 B1,
issued Jun. 5, 2001 (“Abdallah”) and Official Notice.

ISSUES
Based on our review of the administrative record, Appellants’
contentions, and the Examiner’s findings and conclusions, the pivotal issue
before us follows:
Does the Examiner err in finding that AltiVec discloses “a hardware
execution unit for executing a tree-add instruction so as to write an n-bit
result in said result register, said n-bit result having a magnitude equal to a
magnitude of a sum of at least p addends” within the meaning of Appellants’
claim 15 and commensurate limitations of claim 20?

FINDINGS OF FACT
We adopt the Examiner’s findings in the Answer and the Final Office
Action mailed April 21, 2010, as our own, except as to those findings that
we expressly overturn or set aside in the Analysis that follows.

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ANALYSIS
Based on Appellants’ arguments (App. Br. 13-20), we select
independent claim 15 as representative of Appellants’ arguments and
groupings with respect to claims 15, 16, 18-21, 23, and 24. 37 C.F.R.
§ 41.37(c)(1)(iv).
The § 102 Rejection - Claim 15
Appellants contend that AltiVec does not disclose the features recited
in claim 15. (App. Br. 13-16; Reply Br. 3-4.) Specifically, Appellants
contend that “[t]he term ‘sum’ is defined as a limited precision arithmetic
sum in the specification” and “AltiVec’s disclosure of a ‘saturated sum’ . . .
does not meet the foregoing definition.” (App. Br. 13.)
The Examiner sets forth a detailed explanation of the anticipation
rejection in the Examiner’s Answer with respect to each of the claims so
rejected (Ans. 3-4, 11-14) and, in particular, the rejection of claim 15 (Id.)
Specifically, the Examiner provides a detailed explanation with respect to
how Appellants’ claim limitations read on AltiVec’s saturated sum. (Ans.
11-14.) We adopt these findings and this reasoning as our own.
Upon consideration of the evidence on this record and each of
Appellants’ contentions, we find that the preponderance of evidence on this
record supports the Examiner’s findings that AltiVec discloses the disputed
features of claim 15. Accordingly, we sustain the Examiner’s rejection of
claim 15 for the reasons set forth in the Answer, which we incorporate
herein by reference. (Ans. 3-4, 11-14.) Our additional analysis will be
limited to the following points of emphasis.
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We initially note the argued limitation fails to distinguish the claimed
invention from the prior art either structurally or functionally. Specifically,
the recited feature argued by Appellants – “a hardware execution unit for
executing a tree-add instruction so as to write an n-bit result in said result
register, said n-bit result having a magnitude equal to a magnitude of a sum
of at least p addends”) (claim 15 (emphasis added)) – essentially consists of
a statement of intended use or purpose of the recited sum result, which is
merely data –i.e., non-functional descriptive material. The intended use
does not change the structure of the recited hardware execution unit or the
recited registers and, in this instance, does not further limit the scope of the
claim. See Boehringer Ingelheim Vetmedica, Inc. v. Schering-Plough Corp.,
320 F.3d 1339, 1345 (Fed. Cir. 2003) (a statement of intended use “usually
will not limit the scope of the claim because such statements usually do no
more than define a context in which the invention operates”).
Further, the recited “sum” is essentially non-functional descriptive
material in that the limitation simply recites writing a result in a register
which is simply data. The information (data) intended to be written
constitutes non-functional descriptive material, which merely recites what
the information or data represents (the name or label for the data). The
recited structure and functionality remain the same regardless of what the
data constitutes, how the data may be named, or the relationship among the
data and do not further limit the claimed invention either functionally or
structurally. The informational content of the data thus represents non-
functional descriptive material, which “does not lend patentability to an
otherwise unpatentable computer-implemented product or process.” Ex
parte Nehls, 88 USPQ2d 1883, 1889 (BPAI 2008) (precedential). See Ex
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parte Curry, 84 USPQ2d 1272, 1274 (BPAI 2005) (informative) (Fed. Cir.
Appeal No. 2006-1003), aff’d, (Rule 36) (June 12, 2006) (“wellness-related”
data in databases and communicated on distributed network did not
functionally change either the data storage system or the communication
system used in the claimed method). See also In re Ngai, 367 F.3d 1336,
1339 (Fed. Cir. 2004); Nehls, 88 USPQ2d at 1887-90 (discussing non-
functional descriptive material).
Even if we arguendo ascribe some patentable weight to the limitation,
we do not read limitations from the Specification into the claims. “Though
understanding the claim language may be aided by explanations contained in
the written description, it is important not to import into a claim limitations
that are not part of the claim.” Superguide Corp. v. DirecTV Enterprises,
Inc., 358 F.3d 870, 875 (Fed. Cir. 2004). Appellants’ arguments concerning
the sum (App. Br. 13-15) urges us to do just this – to read in limitations from
the Specification not recited in the claims.
Further, as explained by the Examiner, AltiVec discloses a “sum” is
identical to Appellants’ result (“sum”) when an overflow condition does not
exist. (See Ans. 11-14.)
Thus, Appellants do not persuade us of error in the Examiner’s
anticipation rejection of representative independent claim 15 or independent
claim 20, which includes limitations of commensurate scope, and is not
separately argued with particularity. (App. Br. 16.) Accordingly, we affirm
the Examiner’s anticipation rejection of claims 15 and 20.
The § 103 Rejection of Claim 15
Appellants contend that Abdallah does not teach the features recited in
claim 15 and it would not have been obvious to modify Abdallah to include
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such features – i.e., “a hardware execution unit for executing a tree-add
instruction so as to write an n-bit result in said result register, said n-bit
result having a magnitude equal to a magnitude of a sum of at least p
addends” (claim 15). (App. Br. 17-20; Reply Br. 5-10.) Specifically,
Appellants contend that “[w]hile Abdallah does not teach the claimed tree-
add instruction, Abdallah does disclose an analogous ‘parallel-add
horizontal’ PADDH operation. Abdallah teaches that the PADDH operation
can be used as the third of a sequence of three component operations used in
executing a parallel sum of absolute differences (PSAD) instruction.” (App.
Br. 17.) Appellants further contend that it would not have been obvious “to
modify Abdallah so that each of the three component operations would be a
separate instruction” (id.) and the Examiner “fails to [provide] a sufficient
motivation or other reason for the proposed combination” (App. Br. 18).
The Examiner sets forth a detailed explanation of the obviousness
rejection of the claims so rejected (Ans. 5-10, 14-17) and, in particular,
claim 15 (Ans. 5-8, 14-17). Specifically, the Examiner explains that
Abdullah discloses a parallel sum of absolute differences (PSAD)
instruction, which includes a parallel-add horizontal (PADDH) operation,
which in turn performs the same functionality as the claimed tree-add
instruction. Appellants concur with the Examiner’s findings – “Abdallah
does disclose an analogous ‘parallel-add horizontal’ PADDH operation.”
(App. Br. 17.) The Examiner further explains that it would have been
obvious to implement the PADDH operation as an instruction. (Ans. 7-8,
14-17.) We adopt these findings and this reasoning as our own.
Upon consideration of the evidence on this record and each of
Appellants’ contentions, we find that the preponderance of evidence on this
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record supports the Examiner’s findings and conclusion that Abdallah would
have at least suggested the disputed features of claim 15. Accordingly, we
sustain the Examiner’s rejection of representative independent claim 15 for
the reasons set forth in the Answer, which we incorporate herein by
reference. (Ans. 5-8, 14-17.) Our additional analysis will be limited to the
following points of emphasis.
As with claim 1 (supra), the argued limitation fails to distinguish the
claimed invention from the prior art either structurally or functionally
because it consists of a statement of intended use or purpose of the recited
“instruction.” Even if we arguendo ascribe some patentable weight to the
limitation, we agree with the Examiner and find that the functionality of the
tree-add instruction is disclosed by Abdallah’s PADDH operation (see
supra). Thus we conclude that Abdallah’s disclosure would have at least
suggested the recited instruction. Appellants’ argument does not take into
account what the prior art would have suggested to one of ordinary skill in
the art – “The test for obviousness is not whether the features of a secondary
reference may be bodily incorporated into the structure of the primary
reference . . . . Rather, the test is what the combined teachings of the
references would have suggested to those of ordinary skill in the art.” In re
Keller, 642 F.2d 413, 425 (CCPA 1981) (citations omitted, emphasis added).
Thus, Appellants do not persuade us of error in the Examiner’s
obviousness rejection of representative claim 15, independent claim 20,
which includes limitations of commensurate scope, and dependent claims
16, 18, 19, 21, 23, and 24 not separately argued with particularity. (App. Br.
20.) Accordingly, we affirm the Examiner’s obviousness rejection of
claims 15, 16, 18-21, 23, and 24.
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CONCLUSIONS OF LAW
Appellants have not shown that the Examiner erred in rejecting claims
15 and 20 under 35 U.S.C. § 102(b).
Appellants have not shown that the Examiner erred in rejecting claims
15, 16, 18-21, 23, and 24 under 35 U.S.C. § 103(a).

DECISION
We affirm the Examiner’s rejections of claims 15, 16, 18-21, 23, and
24.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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