Ex Parte Lee

Board of Patent Appeals and Interferences

Nov 22, 2010

10993583 (B.P.A.I. Nov. 22, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/993,583 11/19/2004 Thomas Anthony Lee X-1654 US 2221
24309 7590 11/23/2010
XILINX, INC
ATTN: LEGAL DEPARTMENT
2100 LOGIC DR
SAN JOSE, CA 95124
EXAMINER
DANG, KHANH
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
11/23/2010 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte THOMAS ANTHONY LEE
____________________

Appeal 2009-006999
Application 10/993,583
Technology Center 2100
____________________

Before ANTON W. FETTING, JOSEPH A. FISCHETTI, and
THU A. DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

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Application 10/993,583

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I. STATEMENT OF CASE
Appellant appeals the Examiner’s final rejection of claims 1-30 under
35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

A. INVENTION
According to Appellant, the invention “relates generally to integrated
circuits, and in particular, to an integrated circuit having a plurality of data
transceivers, and a method of positioning circuit elements on an integrated
circuit” (Spec. 1, ¶ [0001]).

B. ILLUSTRATIVE CLAIMS
Claims 1 and 16 are exemplary and reproduced below:

1. An integrated circuit formed on a substrate and
having a plurality of data transceivers, said integrated circuit
comprising:

a plurality of circuit elements of data transceivers formed
in said substrate and positioned in a column extending in a first
direction on an end of said integrated circuit, wherein said
plurality of circuit elements in said column comprises analog
circuit elements positioned in a sub-column closer to the end of
said integrated circuit than digital circuit elements positioned in
a sub-column;

a plurality of circuit elements formed in said substrate
and positioned adjacent to said plurality of circuit elements of
data transceivers;

a plurality of buses, each bus comprising conductors
extending in said first direction across said plurality of circuit
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elements of each data transceiver of said plurality of data
transceivers over a portion of said substrate having said
plurality of circuit elements of data transceivers; and

a plurality of interconnect elements providing
connections between said plurality of circuit elements of data
transceivers formed in said substrate and said plurality of circuit
elements formed in said substrate and positioned adjacent to
said plurality of circuit elements of data transceivers.

16. An integrated circuit having a plurality of data
transceivers, said integrated circuit comprising:

a plurality of data transceivers positioned in a first
column extending between a top to a bottom on a first end of
said integrated circuit and having a plurality of circuits arranged
in sub-columns extending between said top to said bottom in a
first configuration of sub-columns with respect to a first end,
each sub-column of said first configuration comprising circuits
having different functionality;

a plurality of programmable logic blocks enabling
programmable logic functions of said integrated circuit, said
plurality of programmable logic blocks arranged in columns
and coupled to said first plurality of data transceivers; and

a second plurality of data transceivers positioned in a
second column extending between said top to said bottom on a
second end of said integrated circuit opposite said first end and
having a plurality of circuits arranged in sub-columns extending
between said top to said bottom in a second configuration of
sub-columns with respect to said second end which is different
than said first configuration of sub-columns with respect to said
first end, each sub-column of said second configuration
comprising circuits having different functionality, said second
plurality of data transceivers being coupled to said plurality of
programmable logic blocks.

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C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Yancey US 2005/0256969 A1 Nov. 17, 2005

Claims 1-30 stand rejected under 35 U.S.C. § 112, first paragraph, as
failing to comply with the written description requirement.
Claims 1-15 and 26-30 stand rejected under 35 U.S.C. § 112, second
paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which Applicant regards as the invention.
Claims 1-30 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Yancey.

II. ISSUES
1. Has the Examiner erred in finding that the term “conductors”
(claim 1) does not have support from the originally filed Specification?
2. Has the Examiner erred in finding that the term “conductors”
(claim 1) is unclear?
3. Has the Examiner erred in finding that Yancey discloses an
integrated circuit comprising “a plurality of circuit elements of data
transceivers formed in said substrate and positioned in a column extending
in a first direction on an end of said integrated circuit” and “a plurality of
buses, each bus comprising conductors extending in said first direction
across said plurality of circuit elements of each data transceiver of said
plurality of data transceivers over a portion of said substrate having said
plurality of circuit elements of data transceivers” (claim 1)? In particular,
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the issue turns on whether Yancey teaches an integrated circuit comprising a
bus comprising conductors extending thereon.
4. Has the Examiner erred in finding that Yancey discloses “a
plurality of circuits arranged in sub-columns extending between said top to
said bottom” (claim 16)? In particular, the issue turns on whether Yancey
teaches circuits arranged in sub-columns.

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Yancey
1. Yancey discloses a duplex data communication link formed between a
plurality of Field Programmable Gate Arrays (FPGAs) to provide
communication between the FPGAs (Figs. 2 & 3; ¶ [0038]).
2. Each FPGA including a plurality of Multi-Gigabyte Serial Transceiver
(MGT) connection cores 210 (each connection core including
respective MGT transmitter 312 and MGT receiver 314) that form
duplex data communication link 300 (id.).
3. Connection core 210 is configured with a plurality of circuitries (Fig.
4; ¶¶ [0041]-[0045]).

IV. ANALYSIS
§ 112, First Paragraph
The Examiner finds that “the term ‘conductors’ in ‘each bus
comprising conductors extending in said first direction’ does not have
support from the originally filed [S]pecification” (Ans. 3). Though
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“Applicant[] referred to Figs. 4 and 5,” the Examiner notes that “the
drawings are used for illustration purpose only and cannot be used to replace
a detailed description of the invention” (id.).
We disagree with the Examiner that the drawings are for illustration
purpose only, where they are used, not to replace the detailed description,
but rather to supplement the detailed description. In particular, we agree
with Appellant and find that the Specification at [0023]-[0027] provides
support for the limitation. In particular, [0023] describes that “the first 5
layers 306 could comprise conductors” wherein “[e]ven layers of the
interconnect layers could be used to route signals in a longitudinal direction,
while odd layers could be used to route signals in a lateral direction.”
Figures 4 and 5 supplement such description. Thus, we are persuaded that
the Examiner erred in concluding that claims 1-30 do not have support from
the originally filed specification as required by 35 U.S.C. § 112, first
paragraph.
§ 112, Second Paragraph
In view of the § 112, second paragraph rejection of claims 1-30, the
Examiner finds that “[it] is unclear what may be ‘conductors’” (Ans. 4).
However, we do not find the term “conductors” to be unclear. We are
persuaded that the Examiner erred in concluding that claims 1-15 and 26-30
are indefinite under 35 U.S.C. § 112, second paragraph.
35 U.S.C. § 102
As to claims 1, 6, 11, and 26, Appellant argues that “the connections
between the separate integrated circuits, shown by way of example in Fig. 3
as FPGAs, are clearly card-level connections between integrated circuits”
and thus “connections between the FPGAs of Fig. 3 in Yancey do not
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disclose a plurality of buses of an integrated circuit as claimed” (App. Br.
15).
The Examiner responds that “Yancey discloses a single integrated
circuit (IC) 100 comprising a plurality of FPGAs (Field Programmable Gate
Array) 102-108” (Ans. 22) (emphasis omitted), wherein “Yancey discloses a
plurality of buses, each bus 300 comprising conductive wires for carrying
serial signals 318 and 320 to provide conductive connections between circuit
elements” (id. at 24).
After reviewing the record on appeal, we agree with the Appellant that
Yancey fails to disclose an integrated circuit comprising “a plurality of
circuit elements of data transceivers formed in said substrate and positioned
in a column extending in a first direction on an end of said integrated
circuit” and “a plurality of buses, each bus comprising conductors extending
in said first direction across said plurality of circuit elements of each data
transceiver of said plurality of data transceivers over a portion of said
substrate having said plurality of circuit elements of data transceivers” as
required by claim 1.
Yancey discloses a duplex data communication link formed between a
plurality of FPGAs (integrated circuits) to provide communication between
the FPGAs (FF 1). In particular, the communication links of Yancey
interconnect the plurality of integrated circuits, and do not connect the
circuit elements of an individual integrated circuit.
Though the Examiner finds that “Yancey discloses a single integrated
circuit (IC) 100” (Ans. 22) (emphasis omitted), the circuit card 100 of
Yancey is not an integrated circuit but rather a card comprising a plurality of
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integrated circuits. Thus, the communication links in the sections of Yancey
pointed out by the Examiner serve to interconnect the plurality of integrated
circuits, and cannot be interpreted to be “buses” of an integrated circuit that
comprise conductors extending in the first direction across the plurality of
circuit elements on an end of the integrated circuit. We cannot find any
teaching of buses connecting the circuit elements on the integrated circuits
themselves in the sections of Yancey referenced by the Examiner.
Thus, the Examiner erred in finding claim 1 anticipated by Yancey.
Accordingly, we reverse the rejection of claim 1, claims 6, 11 and 26
standing with claim 1, and claims 2-5, 7-10, 12-15, and 27-30 depending
respectively therefrom under 35 U.S.C. § 102(e) over Yancey.
As to claims 16 and 21, Appellant merely contends that “there is no
statement in the Office Action as to how Yancey discloses sub-columns, or
how the configuration of sub-columns is different in two columns on
opposite sides of the integrated circuit” (App. Br. 18).
However, the Examiner finds “Fig. 2 [of Yancey] shows a plurality of
data transceivers MGT 210 positioned in a column extending between a top
to a bottom on a first end of an integrated circuit” (Ans. 28). Further, the
Examiner finds Yancey discloses that “a plurality of analog and digital
circuits having different functionalities . . . of a plurality of data transceivers
are arranged in sub-columns extending from the top to bottom” (id.).
According to the Examiner, “the so-called ‘first-end’ of the integrated circuit
is different than the ‘second end’ of the integrated circuit due to the fact that
an integrated circuit [sic] has multiple ends depending on how one defines
an ‘end’ of the integrated circuit” (Ans. 29). The Examiner also finds that
“the term ‘opposite’ is only a relative term and it is clear that the first end of
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the [integrated circuit], depending on a reference location of a particular
portion/section of the first end, is opposite to the second end” (id.).
To determine whether Yancey teaches an integrated circuit
comprising “a plurality of data transceivers positioned in a first column
extending between a top to a bottom on a first end of the integrated circuit
and having a plurality of circuits arranged in sub-columns extending
between said top to said bottom” as required by claim 16, we give the claim
its broadest reasonable interpretation. See In re Bigio, 381 F.3d 1320, 1324
(Fed. Cir. 2004). We note that claim 16 does not place any limitation on
what “column” or “sub-column” means, includes, or represents, other than
reciting that the data transceivers and circuits are positioned in columns and
sub-columns, respectively. We thus give “column” (similarly “sub-
column”) its ordinary meaning of a line of units, wherein the number of
units can vary from 0 to infinite.
Similarly, since claim 16 also does not place any limitation on what
an “end” means, includes or represents, we also give the term its broadest
but reasonable interpretation of any section that is not the center of the
integrated circuit.
In Yancey, each FPGA includes a plurality of data transceivers
extending across an integrated circuit (FF 2) and a plurality of circuits
extending therebetween (FF 3). We see no error in the Examiner’s finding
that “Fig. 2 [of Yancey] shows a plurality of data transceivers MGT 210
positioned in a column extending between a top to a bottom on a first end of
an integrated circuit” (Ans. 28) and that “a plurality of analog and digital
circuits having different functionalities . . . of a plurality of data transceivers
are arranged in sub-columns extending from the top to bottom” (id.). That
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is, we agree with the Examiner an integrated circuit “has multiple ends
depending on how one defines an ‘end’ of the integrated circuit” and “the
term ‘opposite’ is only a relative term” (Ans. 29).
Appellant provides no response to such Examiner’s findings. Thus,
Appellant has not shown where the Examiner erred in finding claim 16 and
claim 21 falling therewith anticipated by Yancey.
Thus, the Examiner has not erred in finding claims 16 and 21
anticipated by Yancey. Accordingly, we affirm the rejection of claims 16
and 21, and claims 17-20 and 22-25 depending respectively therefrom under
35 U.S.C. § 102(e) over Yancey.

V. CONCLUSIONS AND DECISION
The Examiner’s decision rejecting claims 16-25 under 35 U.S.C.
§ 102(e) is affirmed. However, the Examiner’s decision rejecting claims 1-
30 under 35 U.S.C. § 112, first paragraph, rejecting claims 1-15 and 26-30
under 35 U.S.C. § 112, second paragraph, and rejecting claims 1-15 and 26-
30 under 35 U.S.C. § 102(e) is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

Appeal 2009-006999
Application 10/993,583

11

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XILINX, INC
ATTN: LEGAL DEPARTMENT
2100 LOGIC DR
SAN JOSE, CA 95124