Ex Parte Lee

Board of Patent Appeals and Interferences

Mar 21, 2012

10453226 (B.P.A.I. Mar. 21, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/453,226 06/02/2003 Hee Choul Lee I4303.0232 9510
38881 7590 03/21/2012
DICKSTEIN SHAPIRO LLP
1633 Broadway
NEW YORK, NY 10019
EXAMINER
PATEL, HETUL B
ART UNIT PAPER NUMBER
2186
MAIL DATE DELIVERY MODE
03/21/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte HEE CHOUL LEE
____________________
Appeal 2011-0089991
Application 10/453,226
Technology Center 2100
____________________

Before JOSEPH L. DIXON, JEAN R. HOMERE, and
ST. JOHN COURTENAY III, Administrative Patent Judges.

HOMERE, Administrative Patent Judge

DECISION ON APPEAL

1 Filed June 02, 2003. The real party in interest is Infineon Technologies
AG. In an earlier Opinion (2009-000756), we affirmed the Examiner’s
rejection of claims 1-12 as being anticipated by Hass.
Appeal 2011-008999
Application 10/453,226

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I. STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134(a) from the final rejection of
claims 1 through 12. Claims 13 through 20 have been withdrawn from
consideration. Claims 21 and 22 have been canceled. (App. Br. 2.) We have
jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellant’s Invention
Appellant invented a multithreaded processor (200) that uses a
processing core (210) to execute a plurality of active threads independently
of one another. Spec. 2, (Para. [0007].) On one side, the processing core
(210) is coupled to a global program micro-cache (220) and a plurality of
thread program micro-caches (225). On the other side, the processing core
(210) is coupled to a global data micro-cache (240) and a plurality of thread
data micro-caches (245). Spec., 4, (Para. [0017].) Each of the processor
threads is assigned to a different thread micro-cache so that the execution of
a current thread does not interfere with the data or program instructions of a
previous thread. (Fig. 2, Spec. 4, (Para. [0016].)

Illustrative Claim
Independent claim 1 further illustrates the invention. It reads as
follows:
1. A cache system for a multithreaded processor having a single
processing core and a plurality of active threads, the cache system
comprising:
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Application 10/453,226

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a first thread micro-cache directly coupled to the single processing
core; and

a second thread micro-cache directly coupled to the single processing
core,

wherein the first thread micro-cache is assigned a first active thread
and the second thread micro-cache is assigned a second active thread.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Dutton US 5,944,816 Aug. 31, 1999
Frank US 6,021,470 Feb. 01, 2000
Joy US 6,542,991 B1 Apr. 1, 2003
Hass US Patent Pub. No.: 2004/0103248 A1 May 27, 2004
(Provisionally filed Oct. 8, 2002)

Choi US 7,516,446 B2 Apr. 7, 2009
(Filed Jun. 25, 2002)

Rejections on Appeal
The Examiner rejected the claims on appeal as follows:
1. Claims 1 and 9 stand rejected as being anticipated by Joy.
2. Claims 1, 2, 4-6, 9 and 10 stand rejected as being unpatentable over
the combination of Hass and Joy.
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Application 10/453,226

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3. Claims 1, 2, 4-6, 9, and 10 stand rejected as being unpatentable over
the combination of Hass and Choi.
4. Claims 3 and 8 stand rejected as being unpatentable over the
combination of Hass, Joy and Frank.
5. Claims 7, 11, and 12 stand rejected as being unpatentable over the
combination of Hass, Choi, and Dutton.

ANALYSIS
Dispositive Issue: Has Appellant shown that the Examiner erred in
finding that Hass or Joy, taken alone or in combination with Choi, discloses
a first micro cache and second micro cache, each being directly coupled to a
single processing core, as recited in amended claim 1?
Appellant argues that neither Hass, Joy, Choi, nor any combination
thereof discloses the disputed limitations emphasized above. (App. Br. 3-7,
Reply Br. 1-2.) According to Appellant, while Choi discloses a
multithreaded processor that uses a separate cache for each thread, it is silent
as to whether the thread caches are directly connected to the processor.
(App. Br. 3-5, Reply Br. 1-2.) Further, Appellant argues that while Joy
discloses a multithreaded processor in Figure 3 and a multi-threaded cache
in Figure 7A, it does not disclose a single embodiment that shows how the
cache operates with the processor. (App. Br. 5-7.)
The Examiner finds that because Choi does not place a cache between
thread and the cache being accessed, the cache must be directly coupled to
the thread. (Ans. 20.) Further, the Examiner finds that because Joy does not
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expressly disclose figures 3 and 7A as separate embodiments, they must
form a single embodiment. (Id.)
We note at the outset that both Appellant and the Examiner do not
dispute our finding in the earlier Opinion that Hass discloses a processor
core having a threaded cache directly couple thereto, and at least another
threaded cache being indirectly coupled thereto. (Op. 8.) The dispute here
arises, however, as to whether the prior art currently relied upon by the
Examiner discloses a single processor core having directly coupled thereto a
first data cache and a second data cache. We conclude that it does not.
We do not agree with the Examiner’s conclusory statement that
because Choi does not disclose another cache between the processor and the
threaded cache being accessed, the cache must be directly coupled thereto.
In our view, Choi’s silence with regard to whether the data cache is directly
connected as to the processor can only serve as evidence of what it does not
describe or teach, and not what it does. Similarly, we find Joy’s silence as to
how the processor operates with the multithreaded cache can only show
what Joy fails to describe or teach, as opposed to an inference of what it
does. Additionally, Frank and Dutton fail to remedy the noted deficiencies.
Consequently, we agree with Appellant that the prior art of record does not
describe, teach, or suggest a single multithreaded processor directly coupled
with a first micro cache and a second micro cache. Because Appellant has
shown at least one error in the Examiner’s rejections of claim 1, we need not
address the merits of Appellant’s other arguments. It follows that Appellant
has shown error in rejecting claim 1 based on the cited prior art.
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Because claims 2-12 also recite the disputed limitations, Appellant has
similarly shown error in the Examiner’s rejection of these claims.

DECISION
We reverse the Examiner’s decision to reject claims 1-12.

REVERSED

Vsh