Ex Parte Lee

Board of Patent Appeals and Interferences

Sep 15, 2010

10902607 (B.P.A.I. Sep. 15, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte VAN HOA LEE
____________________

Appeal 2009-006213
Application 10/902,607
Technology Center 2100
____________________

Before ANTON W. FETTING, JOSEPH A. FISCHETTI, and THU A.
DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-006213
Application 10/902,607

I. STATEMENT OF THE CASE
Appellant appeals from the Examiner’s final rejection of claims 1-36
under 35 U.S.C. § 134(a) (2002). We have jurisdiction under 35 U.S.C.
§ 6(b).

We reverse.

A. INVENTION
According to Appellant, the invention relates handling system reset
exceptions (SRE)s (Spec. 1).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary and is reproduced below:
1. A method in a data processing system for changing a
lock-bits combination in a software lock to resolve a deadlock
of a particular subset of a memory region within the data
processing system, comprising:

receiving a system reset exception;

identifying the lock-bits combination to use in the
software lock, wherein the lock-bits combination is identified
based on a value of system reset exception occurrence bits
retrieved from a memory location; and

updating the software lock that is maintained in another
memory location with the identified lock-bits combination,
wherein updating the software lock allows the data processing
system to resolve the deadlock of the particular subset of the
memory region without resetting the software lock to an initial
state.

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Application 10/902,607

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Taguchi US 7,137,031 B2 Nov. 14, 2006
Worley US 5,596,733 Jan. 21, 1997
Zimmer US 2005/0149711 A1 Jul. 7, 2005
Johnson US 5,398,330 Mar. 14, 1995
Claims 1, 3, 6-9, 11-13, 15, 18-21, 23-25, 27, 30-33, 35 and 36 stand
rejected under 35 U.S.C. § 103(a) as unpatentable over Taguchi in view of
Worley.
Claims 2, 14, and 26 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Taguchi in view of Worley and AAPA.
Claims 4, 16, and 28 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Taguchi in view of Worley and Zimmer.
Claims 5, 10, 17, 22, 29, and 34 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Taguchi in view of Worley and Johnson.

II. ISSUE
Has the Examiner erred in holding that Taguchi in view of Worley
would have suggested “identifying the lock-bits combination to use in the
software lock, wherein the lock-bits combination is identified based on a
value of system reset exception occurrence bits retrieved from a memory
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Appeal 2009-006213
Application 10/902,607

location” and “updating the software lock that is maintained in another
memory location with the identified lock-bits combination, wherein updating
the software lock allows the data processing system to resolve the deadlock”
(claim 1)?

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Taguchi
1. Taguchi discloses a Logical Unit that is configured to permit and
reject I/O accesses, wherein access only from one host is allowed (col.
2, ll. 22-26).
2. For improved security, secondary hosts within the cluster that run the
application processes are thereby not permitted to access the Logical
Unit until they have obtained that right, typically as a result of a
failure in the primary host (col. 2, ll. 35-41).
Worley
3. Worley discloses storing status bits in an exception register as a result
of executing an instruction which indicates a potentially exceptioning
instruction (col. 5, ll. 9-21).

IV. ANALYSIS
Claims
As to claim 1, Appellant argues that Taguchi fails to describe the
limitation of “identifying the lock-bits combination to use in the software
lock, wherein the lock-bits combination is identified based on a value of
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Appeal 2009-006213
Application 10/902,607

system reset exception occurrence bits retrieved from a memory location” of
claim 1. In particular, Appellant contends that, according to the claimed
invention, “the lock bits combination that is used in the software lock is
identified based on a value of system reset exception bits” (App. Br. 13).
The Appellant contends that “a host ID as taught by Taguchi is not in any
way associated with ‘system reset exception occurrence bits’” (id.). The
Appellant also argues that Worley does not “overcome the above mentioned
teaching/suggestion deficiency” (id.).
Though the Examiner finds that the situation in Appellant’s invention “is
exactly the same situation that occurs in the system of Taguchi” because “if
a failure … occurs … a second LU 108B may take over control of the shared
memory … thus avoiding a deadlock” (Ans. 10), after reviewing the record
on appeal, we agree with the Appellant that Taguchi fails to address
resolving a deadlock by identifying the lock bits combination based on a
value of system reset exception bits, as required by claim 1.
Taguchi avoids deadlock by allowing access to only one host at a time,
wherein secondary hosts are permitted to access the Logical Unit after
obtaining access right, following a failure in the primary host (FF 1-2). By
avoiding a deadlock, there will not be a deadlock to be resolved. Thus,
though we agree with the Examiner that Taguchi discloses avoiding
deadlock (Ans. 10), we cannot find any teaching of identifying of lock-bits
combination based on reset exception occurrence bits wherein the software
lock is updated with the identified lock-bits combination and “updating the
software lock allows the data processing system to resolve the deadlock” as
required by claim 1, in the sections referenced by the Examiner. That is,
Taguchi discloses avoiding deadlock but does not disclose resolving
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Application 10/902,607

deadlock by updating the software lock with lock-bits combination
identified based on reset exception occurrence bits.
Furthermore, though Appellant admits that “Worley may describe the
existence of system reset exception occurrence bits” (App. Br. 13), we agree
with Appellant that Worley does not cure the deficiencies of Taguchi (id.).
That is, though Worley may teach a reset exception occurrence bits, we
cannot find any suggestion in either Taguchi or Worley, alone or in
combination of the required “identifying the lock-bits combination to use in
the software lock, wherein the lock-bits combination is identified based on a
value of system reset exception occurrence bits retrieved from a memory
location” and “updating the software lock that is maintained in another
memory location with the identified lock-bits combination, wherein updating
the software lock allows the data processing system to resolve the deadlock”
(claim 1).
As such, we will reverse the rejection of representative claim 1,
independent claims 13 and 25 standing therewith, and 3, 6-9, 11, 12, 15, 18-
21, 23, 24, 27, 30-33, 35 and 36 depending respectively therefrom.
Claims 2, 4, 5, 10, 14, 16, 17, 22, 26, 28, 29, and 34
We also find that AAPA, Zimmer, and Johnson do not cure these
deficiencies of Taguchi and Worley. As such, we will reverse the rejection
of claims 2, 14, and 26 over Taguchi in view of Worley and AAPA, the
rejection of claims 4, 16, and 28 over Taguchi in view of Worley and
Zimmer, and the rejection of claims 5, 10, 17, 22, 29, and 34 over Taguchi in
view of Worley and Johnson.

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Appeal 2009-006213
Application 10/902,607

V. CONCLUSION
Appellant has shown that the Examiner erred in holding claims 1-36
unpatentable under 35 U.S.C. § 103(a).

VI. DECISION
We have not sustained the Examiner's rejection with respect to any
claim on appeal. Therefore, the Examiner’s decision rejecting claims 1-36 is
reversed.

REVERSED

peb

IBM CORP (YA)
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