Ex Parte Lang et al

Patent Trial and Appeal Board

Feb 28, 2018

14247136 (P.T.A.B. Feb. 28, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/247,136 04/07/2014 Tobias LANG BOSC.P8740US/1000199655 3033
24972 7590 03/02/2018
NORTON ROSE FULBRIGHT US LLP
1301 Avenue of the Americas
NEW YORK, NY 10019-6022
EXAMINER
MALZAHN, DAVID H
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
03/02/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
nyipdocket@nortonrosefulbright.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TOBIAS LANG, HEINER MARKERT, AXEL AUE,
WOLFGANG FISCHER, ULRICH SCHULMEISTER, NICO BANNOW,
FELIX STREICHERT, ANDRE GUNTORO, CHRISTIAN FLECK,
ANNE VON VIETINGHOFF, MICHAEL SAETZLER,
MICHAEL HANSELMANN, and MATTHIAS SCHREIBER
Appeal 2017-006073
Application 14/247,1361
Technology Center 2100
Before ERIC B. CHEN, MONICA S. ULLAGADDI, and SCOTT E. BAIN,
Administrative Patent Judges.
ULLAGADDI, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review, under 35 U.S.C. § 134(a), of the
Examiner’s final rejection of claims 1-6, 8, and 9. We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
1 Appellants identify the real party in interest as Robert Bosch GmbH. App.
Br. 2.
Appeal 2017-006073
Application 14/247,136
INVENTION
“The present invention relates to a model calculation unit for a control
unit in which data-based function models for carrying out functions on the
hardware side are implemented.” Spec. 1,11. 3-5. The independent claims
on appeal are claims 1, 6, and 8. Claim 1 is illustrative and reproduced
below with emphasis added to certain disputed limitations.
1. A model calculation unit for calculating a data-based
function model in a control unit, comprising:
at least one processor core which includes:
a multiplication unit for carrying out a multiplication in
hardware;
an addition unit for carrying out an addition in hardware;
an exponential function unit for calculating, in hardware,
exclusively only an exponential function;
a memory in the form of a configuration register for
storing hyperparameters and node data of the data-based
function model to be calculated; and
a logic circuit for controlling, in hardware, a calculation
sequence in the multiplication unit, the addition unit, the
exponential function unit and the memory in order to
calculate the data-based function model.
App. Br. 8 (Claims Appendix).
REJECTIONS
Claims 1, 2, 4-6, and 8 are rejected under 35 U.S.C. § 102(a) as
anticipated by Mortensen (US 2014/0067889 Al; Mar. 6, 2014). Final
Act. 2-3 (Aug. 1, 2016).
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Claim 3 is rejected under 35 U.S.C. § 103 as obvious over Mortensen
and Hattori (US 6,223,196 Bl; Apr. 24, 2001). Final Act. 3.
Claim 9 is rejected under 35 U.S.C. § 103 as obvious over Mortensen
and Azadet (US 2010/0198894 Al; Aug. 5, 2010). Final Act. 3^1.
ANTICIPATION REJECTION OF
CLAIMS 1, 2, 4-6, AND 8 OVER MORTENSEN
Claims 1, 2, and 6
Claim 1 recites, inter alia, “an exponential function unit for
calculating, in hardware, exclusively only an exponential function.”
Reading the claimed exponential function unit on Mortensen’s digital
hardware calculator (DHC) 104, the Examiner finds paragraph 15 discloses
that the DHC is configurable to perform only exponential calculations.
Final Act. 3. Appellants argue:
The Examiner states that Morte[n]sen’s digital hardware
calculator “which can perform multiple functions suggests that it
could be modified to exclusively perform the exponential
function.” However, this statement is without support.
Moreover, even if Morte[n]sen’s calculator “could” be so
modified, Mortensen neither discloses nor suggests such a
modification.
App. Br. 4.
Appellants’ argument is not persuasive. Mortensen discloses that the
DHC “is configured to calculate one [or] more . . . mathematical functions
such as ... an exponent function”. Mortensen 15 (emphasis added). Thus,
Mortensen expressly discloses that the DHC is optionally configured to
exclusively calculate an exponential function.
Claim 1 further recites, inter alia, “a logic circuit for controlling, in
hardware, a calculation sequence in the multiplication unit, the addition unit,
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Application 14/247,136
the exponential function unit and the memory.” The Examiner finds
Mortensen’s device must control the MAC and DHC 104 to utilize “a mix of
multiplication, addition[,] and subtraction operations and . . . hard
mathematical functions[.]” Ans. 2 (quoting Mortensen 15); see Final
Act. 2. Appellants argue:
The Examiner . . . states that[,] because Mortensen can
implement numerous [digital signal processing (DSP)]
algorithms, it “inherently implies” that a control circuit is present
to effect the calculation. However, “a control circuit” which
controls, “in hardware, a calculation sequence” is not necessarily
required to implement the DSP algorithms, and the Examiner has
not established that it is, in fact, required.
Reply Br. 2; see App. Br. 5.
Appellants’ argument is not persuasive. The Examiner finds that
Mortensen’s paragraph 15 teaches a selectable mix of MAC and DHC
functions, and reasons that a circuit must control those selections in
hardware and thereby control the resulting sequence of calculations. Ans. 2;
Final Act. 2. This “control” includes splitting a DSP algorithm’s
computations between hardware resources of Mortensen’s disclosed
datapath circuit. Mortensen 15. We find that the Examiner provides a
teaching and technical reasoning to support the finding that Mortensen
inherently discloses the claimed logic circuit. The Examiner thus establishes
a prima facie case of anticipation based on inherency, and the burden shifts
to Appellants to show that controlling DSP algorithm computations, as
taught by Mortensen, does not require the claimed logic circuit. See In re
King, 801 F.2d 1324, 1327 (Fed. Cir. 1986) (“[A]fter the PTO establishes a
prima facie case of anticipation based on inherency, the burden shifts to
appellant to prove that the subject matter shown to be in the prior art does
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Application 14/247,136
not possess the characteristic relied on.”)(quotation marks and citation
omitted)). Appellants merely allege that a control circuit is “not necessarily
required” to implement a DSP algorithm and fail to support this argument
with sufficient evidence of record. Reply Br. 2 (block-quoted supra)', see
also King, 801 F.2d at 1327 (“It did not suffice merely to assert that Donley
does not inherently achieve enhanced color through interference effects,
challenging the PTO to prove the contrary[.]”).
For the foregoing reasons, we are not persuaded that the Examiner
erred in finding that Mortensen discloses, expressly or inherently, the
“exponential function unit” and “logic circuit” limitations as recited in
independent claim 1, the commensurate limitations recited in independent
claim 6, and the limitation recited in claim 2, which depends from claim 1
and is not separately argued. Accordingly, we sustain the rejections of
claims 1,2, and 6.
Claim 4
Claim 4 depends from claim 1 and recites: “(i) carry out a
multiplication and an addition for a calculation of an input standardization of
the input variables, and (ii) carry out a multiplication and an addition for a
calculation of an output standardization of the output variable.”
In the Appeal Brief, Appellants argue the Examiner does not address
the claimed “input standardization” and “output standardization.” App.
Br. 5. In reply to the Examiner’s response (Ans. 4), Appellants argue:
For the input and output standardization, the Examiner now
apparently relies on the “compression” of the input operands
described in Mortensen in [0055]. . . . Mortensen does not
disclose “[carrying] out a multiplication and an addition” to
determine the alleged standardization. In Mortensen [0055], it
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Application 14/247,136
appears that the compression is performed by mapping the input
operand to a look-up table entry—multiplication and addition to
calculate the compressed value is not disclosed.
Reply Br. 3.
Appellants’ argument is persuasive. Mortensen provides only one
example of the cited operand compression; stating: “The compressor
function maps a numerical range of the input operand, for example +32768
to -32767 for signed 16-bit integer representation, into a smaller numerical
range of compressor output values.” Mortensen 55. We are persuaded by
Appellants’ argument that Mortensen’s compressor function does not “carry
out a multiplication and an addition for a calculation” (claim 4) of the
compressed operand. See App. Br. 2-3. Specifically, we are persuaded that
“compressor function map [ping]” is more indicative of a look-up table
determination than a calculation. Id. (citing Mortensen ^55).
Accordingly, we do not sustain the rejection of claim 4.
Claim 5
Claim 5 indirectly depends from claim 1 and recites: “wherein the
function model provides a calculation of a term ((x)i-u)2, Xi corresponding to
the nodes of the data-based function model and u corresponding to the input
variables, and wherein the logic circuit is configured to carry out the
calculation of the term ((x)i-u)2 with the aid of one of (i) the MAC unit or
(ii) the multiplication unit and the addition unit.”
In the Appeal Brief, Appellants argue that the Examiner’s findings
and the cited portion of Mortensen in paragraph 15 fail to address claim 5’s
“specific features[.]” App. Br. 5-6. The Examiner responds: “[Wjhile this
term [((x)i-u)2] is not explicitly recited in Mortensen[,] the operations that
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Application 14/247,136
are necessary to effect this calculation are disclosed by Mortensen[.]” Ans.
4-5. In reply to the Examiner’s Answer, Appellants argue:
[T]he Examiner [now] admits that Morte[n]sen does not
“explicitly” [(Ans. 4)] describe these features. Morte[n]sen
neither implicitly discloses this feature, nor is this feature
inherent in Morte[n]sen. For example, even if Morte[n]sen’s
system could somehow be adapted to perform this calculation,
Morte[n]sen does not disclose the adaptation for this particular
equation.
Reply Br. 3.
Appellants’ argument is not persuasive. As discussed above,
Mortensen discloses controlling a mix of, among other things, subtraction
operations and an exponent function. Mortensen 15. The disputed claim
limitation —“calculating] . . . ((x)i-u)2 with the aid of. . . the MAC unit”
(claim 5)—is met by the mix of determining the difference of (x)i and u via
a subtraction operation, followed by squaring the difference via an exponent
operation. Mortensen teaches the claimed model calculation unit’s
“adaptation for this particular equation” (Reply Br. 3) by disclosing a device
already configured to perform the claimed operations in the recited
sequence. That is, Mortensen’s device is not merely modifiable to
“provide^ a calculation of a term ((x)i-u)2” (claim 5), but is expressly
disclosed as being capable of calculating the claimed term ((x)i-u)2. See
Typhoon Touch Techs., Inc. v. Dell, Inc., 659 F.3d 1376, 1380 (Fed. Cir.
2011) (stating the Federal Circuit has, in addressing infringement of a
pipelined processor for executing recited functions, “explained that the
apparatus as provided must be ‘capable’ of performing the recited function,
not that it might later be modified to perform that function” (addressing
Microprocessor Enhancement Corp. v. Texas Instruments, Inc., 520
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Application 14/247,136
F.3d 1367, 1375 (Fed. Cir. 2008)); see also Peters v. Active Mfg. Co., 129
U.S. 530, 537 (1889) (“That which infringes, if later, would anticipate, if
earlier.”).
Accordingly, we sustain the rejection of claim 5.
Claim 8
Claim 8 recites, inter alia, “a memory in the form of a configuration
register storing hyperparameters and node data of the data-based function
model to be calculated[.]”2 The Final Office Action cites Mortensen at
Figure 1 and paragraph 15 and finds that the cited portions disclose “a
memory in the form of a configuration register.” Final Act. 2. Appellants
argue:
[T]he Examiner apparently believes that a memory “in the form
of a configuration register and a logic circuit” [(Final Act. 2)]
which stores hyperparameters and node data is inherent to
Mortensen. However, even if such a configuration is possible
. . . , Mortensen neither discloses nor suggests it.
App. Br. 6.
Appellants’ argument is persuasive. Although Figure 1 depicts Input
Data Register X, Y, Z 102, neither Figure 1 nor paragraph 15 of Mortensen
expressly discloses a memory, nor does the Final Action explain how or why
Mortensen’s Input Data Register X, Y, Z 102 inherently discloses “storing
hyperparameters and node data of the data-based function model to be
calculated,” as recited in claim 8. The Final Office Action also does not
address how this claimed feature should be construed. The findings set forth
2 In comparison, claim 1 recites, inter alia, “a memory in the form of a
configuration registerstoring hyperparameters and node data of the
data-based function model to be calculated.”
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in the Final Office Action with respect to claim 8 fail to satisfy the notice
requirement under 35 U.S.C. § 132. See In re Jung, 637 F.3d 1356, 1362
(Fed. Cir. 2011) (notice requirement “is violated when a rejection is so
uninformative that it prevents the applicant from recognizing and seeking to
counter the grounds for rejection”).
Accordingly, we do not sustain the rejection of claim 8.
OBVIOUSNESS REJECTION OF
CLAIM 3 OVER MORTENSEN AND HATTORI
Claim 3 depends from claim 1 and is not separately argued. As
discussed above, the arguments for claim 1 are not persuasive. Accordingly,
we sustain the rejection of claim 3.
OBVIOUSNESS REJECTION OF
CLAIM 9 OVER MORTENSEN AND AZADET
Claim 9 depends from claim 8. The Examiner’s findings regarding
Azadet set forth with respect to claim 9 do not cure the deficiency discussed
above with respect to claim 8. Final Act. 3—4; Ans. 5. Accordingly, we do
not sustain the rejection of claim 9.
DECISION
We affirm the Examiner’s decision to reject claims 1-3, 5, and 6.
We reverse the Examiner’s decision to reject claims 4, 8, and 9.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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