Ex Parte Kwon et al

Patent Trials and Appeals Board

Apr 30, 2019

14469500 - (D) (P.T.A.B. Apr. 30, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/469,500 08/26/2014
24309 7590 05/02/2019
XILINX, INC
ATTN: LEGAL DEPARTMENT
2100 LOGIC DR
SAN JOSE, CA 95124
FIRST NAMED INVENTOR
Woon-Seong Kwon
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
X-4405US 5362
EXAMINER
KOLAHDOUZAN,HAJAR
ART UNIT PAPER NUMBER
2898
NOTIFICATION DATE DELIVERY MODE
05/02/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
xilinxipl @xilinx.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WOON-SEONG KWON and SURESH RAMALINGAM 1
Appeal2018-007949
Application 14/469,500
Technology Center 2800
Before BEYERL YA. FRANKLIN, JEFFREY B. ROBERTSON, and
N. WHITNEY WILSON, Administrative Patent Judges.
FRANKLIN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
1 Appellants identify the real party in interest as Xilinx, Inc.
Appeal2018-007949
Application 14/469,500
Appellants request our review under 35 U.S.C. § 134(a) of the
Examiner's decision rejecting claims 1--4, 6, 8-12, which constitute all the
claims pending in this application. We have jurisdiction over the appeal
under 35 U.S.C. § 6(b ).
Claim 1 is illustrative of Appellants' subject matter on appeal and is
set forth below (with text in bold for emphasis):
1. A stacked silicon interconnect product, comprising:
a substrate-less interposer consisting essentially of a
plurality of metallization layers, wherein at least one
metallization layer includes a plurality of metal segments
separated by dielectric material, the dielectric material selected
from silicon dioxide, SiN, and SiC;
a first die coupled to a first side of the substrate-less
interposer via a first plurality of micro bumps;
a second die coupled to a second side of the substrate-
less interposer via a second plurality of micro bumps, the
second die communicatively coupled to the first die through a
metallization layer of the plurality of metallization layers
without routing through a through-substrate via (TSV); and
a plurality of controlled collapse chip connection (C4)
bumps coupled to the second side of the substrate-less
interposer.
THE REFERENCES
The Examiner relies on the following prior art references as evidence
of unpatentability:
Chou
Konchady
us 2014/0217604
us 2016/0056102
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Aug. 7,2014
Feb.25,2016
Appeal2018-007949
Application 14/469,500
THE REJECTION
Claims 1--4, 6, and 8-12 under 35 U.S.C. § 103(a) are rejected as
being unpatentable over Chou et al. (hereinafter Chou) in view of
Konchady et al. (hereinafter Konchady).
ANALYSIS
We review the appealed rejections for error based upon the issues
identified by Appellants and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) ("[I]t
has long been the Board's practice to require an applicant to identify the
alleged error in the examiner's rejections."). After considering the evidence
presented in this Appeal (including the Examiner's Final Office Action,
Answer, the Appeal Brief, and the Reply Brief), we are persuaded that
Appellants identify reversible error. Thus, we reverse the Examiner's
rejection and add the following primarily for emphasis.
Appellants argue in the Appeal Brief that the cited combination does
not teach or suggest a substrate-less interposer. Appeal Br. 6-9.
In response, the Examiner states that Chou teaches a substrate-less
interposer in Figures 1 and 12 since the end product of Chou is no different
than Appellants' disclosure regarding the interposer. The Examiner states
that Figures 1 and 12 of Chou show alternating parts of dielectric and
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Appeal2018-007949
Application 14/469,500
metal materials without an extra substrate ( citing elements 234 and 220).
Ans. 5-7.
However, as Appellants point out on pages 2-3 of the Reply Brief,
regardless of the names used to describe the components, Chou discloses
these dielectric and metal layers deposited on an interposer 200, which is a
semiconductor or dielectric substrate. Chou, ,r 0015. Appellants state that
Chou does not disclose an interposer that only includes the metal and
dielectric layers 220 and 234. Reply Br. 2. Appellants state that in both Fig.
1 and Fig. 12, element 200 (the semiconductor or dielectric interposer 200)
is disclosed as being present and supporting the dielectric and metal parts.
Appellants state that in particular, the elements 234 and 220 cited by the
Examiner, are disposed on an element 200, which is described as being a
semiconductor or dielectric substrate having through-substrate vias ( as
discussed below). Id. We agree.
Appellants also point out that the Examiner states that Chou does not
go into depth of describing the metal parts 220 when the interposer is a
dielectric material rather than a semiconductor material. Reply Br. 2.
Appellants rightly state that one can only discuss what Chou teaches, which
is through-substrate vias extending through the element 200. Chou, ,r 16.
Appellants state that Chou does not give these parts any name other than
through-substrate vias, which are by definition vias that extend through
a substrate. We agree. Appellants state that in both cases where element
200 is semiconductor material or dielectric material, the element 200 is a
substrate by definition in Chou. Reply Br. 2. Appellants state that Examiner
has not provided any evidence that when the element 200 is made of
dielectric the through-substrate vias are not used and that the two dies would
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Appeal2018-007949
Application 14/469,500
be coupled without routing through the through-substrate vias. Appellants
state that in all disclosed embodiments, the through-substrate vias are
present and described as vias extending through a substrate. Reply Br. 2-3.
We are persuaded by such argument.
In view of the above, we reverse the rejection.
DECISION
The rejection is reversed.
REVERSED
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