Ex Parte Kumar et al

Patent Trial and Appeal Board

Apr 20, 2017

13854879 (P.T.A.B. Apr. 20, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/854,879 04/01/2013 Roger Kumar APLE.P0077DIV 1 7199
62224 7590
ADELI LLP
11859 Wilshire Blvd., Suite 408
LOS ANGELES, CA 90025
EXAMINER
TORRENTE, RICHARD T
ART UNIT PAPER NUMBER
2485
NOTIFICATION DATE DELIVERY MODE
04/24/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
mail@ adelillp.com
PatentOffice @ adelillp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ROGER KUMAR, THOMAS PUN, HSI JUNG WU,
and CHRISTIAN DUVIVIER
Appeal 2017-000497
Application 13/854,8791
Technology Center 2400
Before DEBRA K. STEPHENS, KEVIN C. TROCK, and
JESSICA C. KAISER, Administrative Patent Judges.
TROCK, Administrative Patent Judge.
DECISION ON APPEAL
Introduction
Appellants seek review under 35U.S.C. § 134 from a Final Rejection
of claims 37—43, 45—55, and 57—60. Claims 1—36, 44, and 56 have been
cancelled. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 According to Appellants, the real party in interest is Apple Inc. App. Br. 2.
Appeal 2017-000497
Application 13/854,879
Invention
The claims are directed to a method of processing images in a video
sequence by retrieving image frame tiles corresponding to a block of pixels.
Spec. 26—27, Abstract.
Exemplary Claim
Claim 37, reproduced below, is illustrative of the claimed subject
matter with disputed limitations emphasized:
37. A method for processing a stream comprising a first image
and a second image, the method comprising:
dividing the first image into a set of non-overlapping tiles
to include a plurality of rows of tiles and a plurality of columns
of tiles;
storing the set of tiles in a non-cache memory storage;
when a particular sub-set of the stored set of tiles is needed
to compare a first set of pixels in the first image with a second
set of pixels in the second image, retrieving the particular sub­
set of tiles from the non-cache memory storage, wherein the first
set of pixels overlaps a portion of each tile in the particular sub­
set, wherein the particular sub-set of tiles does not comprise an
entire row or an entire column of tiles of the first image; and
storing the particular sub-set of tiles in a cache memory
storage to compare a third set of pixels in the first image with the
second set of pixels in the second image, wherein the third set of
pixels also correspond to a part of the particular sub-set of tiles.
REFERENCE
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Malladi US 5,912,676
2
June 15, 1999
Appeal 2017-000497
Application 13/854,879
REJECTION
Claims 37-43, 45—55, and 57—602 stand rejected under 35 U.S.C.
§ 102(e) as being anticipated by Malladi. Final Act. 3—6.
ANALYSIS
We have reviewed the Examiner’s rejections and the evidence of
record in light of Appellants’ arguments that the Examiner has erred. We
disagree with Appellants’ arguments and conclusions. We adopt as our own
the findings and reasons set forth by the Examiner in the action from which
this appeal is taken (Final Act. 2—6) and the findings and the reasons set
forth in the Examiner’s Answer (Ans. 6—9). We concur with the conclusions
reached by the Examiner and further highlight specific findings and
argument for emphasis as follows.
Anticipation of Independent Claims 37 and 50
“sub-set of tiles ”
Appellants contend the Examiner erred in finding Malladi discloses
“retrieving the particular sub-set of tiles from the non-cache memory
storage, wherein the first set of pixels overlaps a portion of each tile in the
particular sub-set,” as recited in claim 37 and similarly recited in claim 50.
App. Br. 8—9; Reply Br. 4—5. Specifically, Appellants argue Malladi
discloses “how luma blocks of a macroblock are stored in SDRAM,” rather
than disclosing overlapping pixels and tiles. App. Br. 9 (citing Malladi
2 The Examiner states claims 37—60 have been rejected (Final Act. 3);
however, claims 44 and 56 have been cancelled (App. Br. 20, 22). We
consider this harmless error.
3
Appeal 2017-000497
Application 13/854,879
17:35—40, Figs. 16a, 16c). Further, Appellants argue Malladi “only
retrieves] the region or portion of each block within the shaded block of
Fig. 16a” (Reply Br. 5), i.e., Malladi only retrieves portions of tiles.
We are not persuaded. The Examiner finds, and we agree, Malladi
discloses an image frame divided into macroblocks, i.e., tiles. Ans. 6 (citing
Malladi Fig. 14); Final Act. 3; see Malladi 17:25—39, Figs. 16a, 16c. The
Examiner further finds, and we agree, Malladi discloses a luma prediction
block (or reference block), i.e., a set of pixels, represented as a shaded
region in Figure 16a, overlapping the image’s macroblocks. Ans. 6—7; see
Malladi 17:46—57. The Examiner additionally finds, and we agree, Malladi
retrieves the portion of a macroblock which corresponds to the overlap.
Ans. 6—7; see Malladi 18:12—26. That is, the entire macroblock is not
retrieved; rather, only the portion of the macroblock corresponding to the
luma prediction block overlap is retrieved.
Appellants’ argument that Malladi’s storage of blocks in memory
does not disclose an overlap of pixels and tiles (App. Br. 9) does not address
the Examiner’s finding that Malladi’s luma prediction block overlaps
Malladi’s macroblocks (Ans. 6—7; see Malladi Figs. 16a, 16c; see also
Malladi 17:4—9, 25—60). Furthermore, Appellants’ argument that Malladi
only retrieves a portion of a block (Reply Br. 5) is not commensurate with
the scope of the claim. The claim does not recite language precluding
portions of tiles from the claimed sub-set of tiles; that is, the claim does not
require the retrieved sub-set of tiles to be whole tiles. Furthermore, the
Specification does not include any express definition requiring that the
retrieved sub-set of tiles are whole tiles, or otherwise explicitly defining
“sub-set.” Therefore, we agree with the Examiner’s broad, but reasonable,
4
Appeal 2017-000497
Application 13/854,879
interpretation that the retrieved portions of Malladi’s macroblocks disclose a
retrieved sub-set of tiles. Accordingly, we are not persuaded the Examiner
erred in finding Malladi discloses “retrieving the particular sub-set of tiles
from the non-cache memory storage, wherein the first set of pixels overlaps
a portion of each tile in the particular sub-set,” within the meaning of claims
37 and 50.
“a cache memory ”
Appellants contend the Examiner erred in finding Malladi discloses
“storing] the particular sub-set of tiles in a cache memory storage,” as
recited in claim 37 and similarly recited in claim 50. App. Br. 9—12; Reply
Br. 6—7. Specifically, Appellants argue the Examiner relies on Malladi’s
VSHELL to store tiles, but “none of the components of the VSHELL 222 is
cache memory” (App. Br. 9—10) and, in particular, the VSHELL’s pre-fetch
buffer is not a cache memory (Reply Br. 6—7).
Initially, we note Appellants have not challenged the Examiner’s
interpretation that a “cache is a hardware or software component that stores
data for future requests so that data can be served faster” (Ans. 7; see Reply
Br. 6-7).
Appellants’ arguments that Malladi’s pre-fetch buffer is not a cache
because “Malladi does not expressly disclose that the pre[-]fetch buffer is
faster” (Reply Br. 6) is not persuasive. The Examiner finds, and we agree,
Malladi’s VSHELL includes “pre-fetch buffer 315” which stores data
retrieved from external memory 204. Ans. 7; see Malladi 11:44—60. Indeed,
Malladi’s “pre-fetch buffer 314 is used to store data being fetched from the
external memory 204 before [it is] provided to the MBCORE 304.” Malladi
5
Appeal 2017-000497
Application 13/854,879
11:58—60. That is, Malladi’s pre-fetch buffer retrieves and stores data to
serve future MBCORE requests, i.e., caches data. Furthermore, the
Examiner finds, and we agree, Malladi’s pre-fetch buffer serves data
requests faster “because retrieval [from] integrated or internal memory is
faster than retrieving from an external memory.” Ans. 7 (emphasis omitted).
Indeed, when the VSHELL’s MBCORE requests data, the MBCORE
receives data directly from the VSHELL’s internal pre-fetch memory 314,
rather than from the external memory 204, resulting in faster data service.
See Malladi Figs. 5—6, 11:44—60. As such, Appellants have not persuaded
us the Examiner erred in finding Malladi’s pre-fetch buffer discloses a cache
because the pre-fetch buffer stores data for future data requests, providing
faster data retrieval (than retrieval from Malladi’s external memory).
Accordingly, we are not persuaded the Examiner erred in finding “storing]
the particular sub-set of tiles in a cache memory storage,” within the
meaning of claims 37 and 50.
Anticipation of Independent Claims 43 and 55
“processing operations ”
Appellants contend the Examiner erred in finding Malladi discloses
identifying a set of pixels in the picture during a first round of
processing operations; identifying a set of tiles associated with
the identified set of pixels . . . wherein the groups of pixels
associated with the identified set of tiles are stored in non-cache
memory; and storing the group of pixels associated with each
identified tile in a cache memory for use in a second round of
said processing operations,
as recited in claim 43 and similarly recited in claim 55. App. Br. 12—16;
Reply Br. 7—8. Specifically, Appellants argue Malladi “do[es] not show tiles
6
Appeal 2017-000497
Application 13/854,879
stored for two different rounds of processing operations.” App. Br. 13
(citing Malladi 17:25—29, 35—37, Figs. 16a, 16c). Further, Appellants argue
“Fig. 14 and the SDRAM 204 in Fig. 5” of Malladi do not identify a set of
pixels in a first round of processing. Reply Br. 7. According to Appellants,
Malladi’s shaded block is not “stored in pre[-]fetch memory,” nor is it stored
in “a cache memory for used in a second round” of processing. Reply Br. 7
(emphasis omitted); App. Br. 13.
We are not persuaded. Appellants’ argument that Malladi “do[es] not
show tiles stored for two different rounds of processing operations” (App.
Br. 13) is not commensurate with the scope of the claim. The claim does not
recite that tiles are stored in two different rounds of processing operations.
Instead, the claim recites during a first processing round, “identifying a set
of pixels.” As discussed supra, we agree with the Examiner’s finding that
Malladi identifies a luma prediction block, i.e., a set of pixels. Final Act. 8
(citing Malladi Fig. 16a); Ans. 7; see Malladi 17:46-47. As to the recited
second processing round “storing the group of pixels,” as discussed supra,
we agree with the Examiner that Malladi retrieves the identified luma
prediction block, i.e., a group of pixels, and stores the retrieved pixels in the
VSHELL’s pre-fetch buffer. Ans. 8 (citing Malladi Fig. 5); see Malladi
11:55-60, 18:12-26.
Further, Appellants’ argument that “Fig. 14 and the SDRAM 204 in
Fig. 5” of Malladi do not identify a set of pixels (Reply Br. 7) is not
responsive to the Examiner’s finding that Fig. 16a of Malladi discloses a
luma prediction block, i.e., an identified a set of pixels, as discussed supra.
Final Act. 5, 8; see Malladi 17:46-47.
7
Appeal 2017-000497
Application 13/854,879
Moreover, Appellants’ argument that Malladi’s luma prediction block
is stored in SDRAM (App. Br. 13; Reply Br. 7) is not responsive to the
Examiner’s finding that Malladi’s VSHELL pre-fetch buffer stores the
retrieved luma prediction block. Ans. 8 (citing Malladi Fig. 5); see Malladi
11:55—60. In particular, Malladi retrieves its luma prediction block from
“frame store memory 204,” i.e., external memory 204 (Malladi 18:3—4) and
Malladi’s “pre-fetch buffer 314 is used to store data being fetched from the
external memory 204” {id. at 11:58—60). That is, Malladi’s retrieval of luma
prediction blocks from external memory 204 stores the luma prediction
blocks in pre-fetch buffer 314, which, as discussed supra, discloses a cache.
Additionally, Appellants repeat their arguments supra, that Malladi
does not disclose pixels overlapping tiles and a cache memory. App. Br.
13—16; Reply Br. 8. We are not persuaded by these arguments for the same
reasons discussed supra.
Accordingly, we are not persuaded the Examiner erred in finding
Malladi discloses
identifying a set of pixels in the picture during a first round of
processing operations; identifying a set of tiles associated with
the identified set of pixels . . . wherein the groups of pixels
associated with the identified set of tiles are stored in non-cache
memory; and storing the group of pixels associated with each
identified tile in a cache memory for use in a second round of
said processing operations,
within the meaning of claims 43 and 55.
Anticipation of Dependent Claims 47, 48, 59, and 60
Appellants contend the Examiner erred in finding Malladi discloses
the “identified sets of pixels comprises at least one non-integer pixel,” as
8
Appeal 2017-000497
Application 13/854,879
recited in claim 47, similarly recited in claim 59, and incorporated into
respective depending claims 48 and 50. App. Br. 17—18; Reply Br. 8—10.
Specifically, Appellants argue Malladi “discloses an interpolated frame and
not an interpolated non-integer pixel.” App. Br. 17. Appellants further
argue “there is no indication (expressly or inherently) that generating the
skewed tile in Malladi requires the [alleged] notoriously well-known
interpolating technique.” Reply Br. 8—9.
We are not persuaded. The Examiner finds, and we agree, Malladi
interpolates pixels because it interpolates frames, which are made of pixels.
Ans. 8—9 (citing Malladi 2:36). The Examiner further finds, and we agree,
that “Malladi shows a skewed tile with the shaded block in fig. 16a” and
“any interpolation performed on skewing a tile will result in a new pixel to
be either integer or non-integer.” Ans. 9.
Appellants’ argument that Malladi does not necessarily need to
generate skewed tiles using interpolation (Reply Br. 8—9) does not address
the Examiner’s finding that one of ordinary skill in the art would understand
that interpolating frames with skewed tiles results in non-integer pixels (Ans.
8—9). Indeed, Malladi discloses an “MPEG stream includes ... the Bi­
directional Interpolated (B) frame” (Malladi 2:36), i.e., Malladi’s MPEG
steam includes interpolated frames. Moreover, Malladi discloses an MPEG
frame with skewed tiles (Malladi 17:25—37, Fig. 16a); accordingly, that
skewed tile MPEG frame would be interpolated, resulting in non-integer
pixels. Therefore, we are not persuaded the Examiner erred in finding
Malladi discloses “identified sets of pixels comprises at least one non­
integer pixel,” within the meaning of claims 47, 48, 59, and 60.
9
Appeal 2017-000497
Application 13/854,879
Remaining Claims 38—42, 45, 46, 49, 51—54, 57, and 58
Appellants do not argue separate patentability for dependent claims
38—42, 45, 46, 49, 51—54, 57, and 58, which depend directly or indirectly
from claims 37, 43, 50, and 55. See App. Br. 8—18. For the reasons set forth
above, therefore, we are not persuaded the Examiner erred in rejecting these
claims. See In reLovin, 652 F.3d 1349, 1356 (Fed. Cir. 2011) (“We
conclude that the Board has reasonably interpreted Rule 41.37 to require
applicants to articulate more substantive arguments if they wish for
individual claims to be treated separately”). Accordingly, we sustain the
Examiner’s decision to reject claims 38-42, 45, 46, 49, 51—54, 57, and 58.
See 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
The Examiner’s rejection of claims 37—43, 45—55, and 57—60 is
AFFIRMED.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv).
AFFIRMED
10