Ex Parte Kuan et al

Board of Patent Appeals and Interferences

May 30, 2012

11276645 (B.P.A.I. May. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/276,645 03/08/2006 Heap Hoe Kuan 27-188 3492
22898 7590 05/30/2012
ISHIMARU & ASSOCIATES LLP
2055 GATEWAY PLACE
SUITE 700
SAN JOSE, CA 95110
EXAMINER
NGO, HUNG V
ART UNIT PAPER NUMBER
2835
MAIL DATE DELIVERY MODE
05/30/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HEAP HOE KUAN, TSZ YIN HO, DIOSCORO A. MERILO,
SENG GUAN CHOW, and ANTONIO B. DIMAANO, JR
____________

Appeal 2010-000038
Application 11/276,6451
Technology Center 2800
____________

Before ST. JOHN COURTENAY III, THU A. DANG, and
CAROLYN D. THOMAS, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is STATS ChipPAC Ltd.
Appeal 2010-000038
Application 11/276,645

2
STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134 of the Examiner’s
final decision rejecting claims 1-20, which are all the claims pending in the
application. We have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
The present invention relates to an integrated circuit package system
for a package on package. See Spec., 1:15.
Claim 1 is illustrative:
1. An integrated circuit leaded stacked package system
comprising:
forming a no-lead integrated circuit package having a
mod cap; and
attaching a mold cap of an extended-lead integrated
circuit package facing the mold cap of the no-lead integrated
circuit package.

Appellants appeal the following rejections:

1. Claims 1, 6-13, 16-18, and 20 are rejected under 35 U.S.C. § 103 (a)
as being unpatentable over Corisis (US 6,607,937 B1, Aug. 19, 2003) and
Sharma (US 6,420,779 B1, Jul. 16, 2002); and
2. Claims 2-5, 14, 15, and 19 under 35 U.S.C. § 103(a) as unpatentable
over Corisis, Sharma, and Matsuzaki (US Patent Pub. No. 2002/0109216
A1, Aug. 15, 2002).

ANALYSIS
Claims 1, 6-13, 16-18, and 20
Appeal 2010-000038
Application 11/276,645

3
Issue 1: Did the Examine err in finding that the combination of
Corisis and Sharma discloses attaching a mold cap of an extended-lead
integrated circuit package facing the mold cap of the no-lead integrated
circuit package, as claimed?

Appellants contend that “Corisis Fig. 3 shows that the Corisis mold
caps 223 are spaced apart and do not touch each other. . . . Sharma Fig. 1
does not teach or suggest that the Sharma mold cap 150 is attached to
anything.” (App. Br. 13.)
The Examiner found that “Corisis discloses attaching a mold cap 222b
of an extended-lead integrated circuit package 220b to a support member
230 facing a mold cap 223 of the no-lead integrated circuit package (Fig. 3).
Furthermore, it is noted that the features upon which applicant relies . . . are
not recited in the rejected claim(s).” (Ans. 7-8.) We agree with the
Examiner.
For example, Corisis discloses two packaged microelectronic devices
positioned proximate to each other and each encased in an encapsulant. (See
Abstract and Fig. 3.) In Corisis, “[b]oth the lower packaged device 220a
and the upper packaged device 220b can include an encapsulating material
223 that at least partially encases the microelectronics dies 224a and 224b.”
(See Corisis, col. 3, ll. 34-37.) In other words, Corisis discloses attaching a
mold cap of a lower packaged device facing the mold cap of an upper
packaged device.

Fig. 3 of Corisis is depicted below:
Appeal 2010-000038
Application 11/276,645

4

Fig. 3 of Corisis illustrates a partially schematic, cross-sectional side view of
a microelectronic device assembly 210 that includes two packaged
microelectronic devices 220.
As shown above, the mold caps (element 223) of both packaged
microelectronic devices are facing each other consistent with the claimed
invention. We find that the term “facing” includes any positional orientation
whereby the components are opposed to each other. As for Appellants
contention that the mold caps of Corisis are not attached to each other (see
App. Br. 13), we conclude that the claimed invention does not require that
the mold caps be attached to each other, only that they are attached so as to
be “facing” each other. (See claim 1.) The claims measure the invention.
See SRI Int’l v. Matsushita Elec. Corp. of America, 775 F.2d 1107, 1121
(Fed. Cir. 1985) (en banc). During prosecution before the USPTO, claims
are to be given their broadest reasonable interpretation, and the scope of a
claim cannot be narrowed by reading disclosed limitations into the claim.
Appeal 2010-000038
Application 11/276,645

5
See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997); In re Zletz, 893 F.2d
319, 321 (Fed. Cir. 1989); In re Prater, 415 F.2d 1393, 1404-05 (CCPA
1969). Here, we shall not read “attached to each other” into the claims.
Therefore, based on the record before us, we find no error in the
Examiner’s obviousness rejection of representative claim 1 essentially for
the reasons indicated by the Examiner. Independent claim11 contains a
similar limitation and is therefore sustained for similar reasons as noted
above. Independent claim 6 does not contain the argued limitation and no
separate argument is presented for claim 6, therefore, we summarily sustain
the rejection of claim 6. Dependent claims 7-10, 12, 13, 16-18, and 20 fall
with their independent claims.
Accordingly, we affirm the rejections of claims 1, 6-13, 16-18, and
20.

Issue 2: Did the Examine err in finding that the combination of
Corisis, Sharma, and Matsuzaki discloses the features as set forth below?

Claims 2 and 3
Appellants contend that, regarding claims 2 and 3, neither Sharma's
Fig. 1 nor Matsuzaki's Fig. 3 teaches or suggest that any semiconductor
package is attached on Sharma package 100 or that Matsuzaki's
semiconductor device 42C is attached ‘on’ semiconductor device 42B.”
(App. Br. 14-15.)
The Examiner found that “Matsuzaki et al. teach the use of a top
integrated circuit package 42d, 42c attached on or positioned above the
extended-lead integrated circuit package 42b(Fig. 3).” (Ans. 8.)
Appeal 2010-000038
Application 11/276,645

6
Fig. 3 of Matsuzuki is depicted below:

Fig. 3 of Matsuzaki illustrates a cross sectional view of four
semiconductor devices 42A, 42B, 42C, and 42D.
Matsuzaki discloses that “the semiconductor device 42B at the second
stage is formed on the top of the semiconductor device 42A with having a
predetermined gap in between.” (Matsuzaki, ¶ [0009].) Claim 2 recites
“attaching a top integrated circuit package on the extended-lead integrated
circuit package.” (See claim 2)(emphasis added.) As such, we find that
Matsuzaki’s “on the top of . . . with having a predetermined gap in between”
is distinguishable from the claimed “on the . . .” Therefore, we find error in
Appeal 2010-000038
Application 11/276,645

7
the Examiner’s obviousness rejection of claim 2, and claim 3 which includes
a similar limitation.
Accordingly, we reverse the rejections of claims 2 and 3.

Claim 4 and 14
Appellants contend that, regarding claims 4 and 14, “Matsuzaki
insulating seal resin 44 . . . is not a separate resin for the lead ends.” (App.
Br. 15.)
The Examiner found that Appellants’ arguments “are not recited in the
rejected claim(s).” (Ans. 7- 8.) We agree with the Examiner.
Claim 4 and 14 require “applying a lead-end encapsulant over the lead
ends of the extended leads,” not using a separate encapsulant for the
extended leads, as argued by Appellants. (See Claim 4 and 14.) As such,
Appellants arguments are not commensurate with the scope of the claims as
the claims do not require a separate encapsulant, and the arguments are
therefore unpersuasive.
Accordingly, we affirm the rejections of claims 4 and 14.

Claims 5 and 15
Appellants contend that, regarding claims 5 and 15, “Corisis . . .
teaches away from Matsuzaki.” (App. Br. 16.)
Appellants evidence that Corisis teaches away from Matsuzaki lies in
the fact that Corisis discloses alternative methods of integrating. However,
we do not find, and Appellants do not establish, that Corisis criticizes,
discredits, or otherwise discourages the use of building up semiconductors as
taught in Matsuzaki. “[T]he prior art's mere disclosure of more than one
Appeal 2010-000038
Application 11/276,645

8
alternative does not constitute a teaching away from any of these alternative
because such disclosure does not criticize, discredit, or otherwise discourage
the solution claimed …” In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004).
“A reference may be said to teach away when a person of ordinary
skill, upon reading the reference...would be led in a direction divergent from
the path that was taken by the applicant.” In re Haruna, 249 F.3d 1327
(Fed. Cir. 2001). We do not find this to be the situation before this Board.
Accordingly, we affirm the rejections of claims 5 and 15.

Claim 19
Appellants have not presented separate arguments for dependent claim
19. (See App. Br. 17.) Therefore, this claim falls with the claim from which
it depends. See 37 C.F.R. § 41.37(c)(1)(vii).

DECISION
We reverse the Examiner’s § 103 rejection of claims 2 and 3.
We affirm the Examiner’s § 103 rejection of claims 1 and 4-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv) .

AFFIRMED-IN-PART

Vsh