Ex Parte Krishnaiyer et al

Patent Trial and Appeal Board

Sep 29, 2017

14273649 (P.T.A.B. Sep. 29, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/273,649 05/09/2014 RAKESH KRISHNAIYER P65941 9511
45459 7590 10/03/2017
GROSSMAN, TUCKER, PERREAULT & PFLEGER, PLLC
1600 Kolb Rd., Suite 118
Tucson, AZ 85715
EXAMINER
TAEUBER, MICHELLE L
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
10/03/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
drobertson@gtpp.com
rmendez@gtpp-tucson.com
intel_docketing @ gtpp .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAKESH KRISHNAIYER, SERGE PREIS,
HIDEKI IDO, and ANATOLY ZVEZDIN
Appeal 2017-006556
Application 14/273,6491
Technology Center 2100
Before ST. JOHN COURTENAY III, MARC S. HOFF, and
JOYCE CRAIG, Administrative Patent Judges.
HOFF, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a Final Rejection of
claims 1—24. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellants’ invention is a processor and method directed to
employing cache memory prefetch to reduce write overhead. If the
processor determines that data to be written to cache memory comprises at
least one cache line to be fully written, the processor will perform a
“prefetch,” writing dummy data to sections of the cache memory
1 The real party in interest is INTEL CORPORATION. App. Br. 1
Appeal 2017-006556
Application 14/273,649
corresponding to the data to be written in full cache lines. The processor
may then write actual data to the sections containing the dummy data,
without the processor first having to verify ownership of the sections. Any
remaining data that will not be written in full cache lines may then be
written to cache memory using a standard write transaction. See Spec.,
Abstract.
Claim 1 is exemplary of the claims on appeal:
1. A processing device, comprising:
a cache memory; and
a processor to:
determine if data to be written to the cache
memory includes data comprising multiple cache lines
wherein at least one of the cache lines will be fully
written;
prepare sections of the cache memory to receive
the data corresponding to the at least one of the cache
lines that will be fully written; and
write at least the data corresponding to the at least
one of the cache lines that will be fully written without
first determining ownership of the sections of the cache
memory.
The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Jim Jeffers et al., Intel® Xeon Ph™ Coprocessor High Performance
Programing, Elsevier (2013), at 122 (hereinafter “Jeffers”).
Nayyar
Kang
Corbal
US 2007/0156980 Al July 15, 2007
US 2013/0297919 Al Nov. 7, 2013
WO 2013/095511 Al June 27, 2013
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Application 14/273,649
Claims 1, 2, 9, 10, 17, and 18 stand rejected under (AIA) 35 U.S.C.
§ 102(a)(1) as being anticipated by Corbal.
Claims 3,4, 11, 12, 19, and 20 stand rejected under (AIA) 35 U.S.C.
§ 103 as being unpatentable over Corbal and Jeffers.
Claims 5, 13, and 21 stand rejected under (AIA) 35 U.S.C. § 103 as
being unpatentable over Corbal and Kang.
Claims 6—8, 14—16, and 22—24 stand rejected under (AIA) 35 U.S.C.
§ 103 as being unpatentable over Corbal and Nayyar.
Throughout this decision, we make reference to the Appeal Brief
(“App. Br.,” filed Sept. 6, 2016), the Reply Brief (“Reply Br.,” filed Mar.
14, 2017), and the Examiner’s Answer (“Ans.,” mailed Jan. 30, 2017) for
their respective details.
ISSUE
Does Corbal disclose “writing at least the data corresponding to the at
least one of the cache lines that will be fully written without first
determining ownership of the sections of the cache memory?”2
ANALYSIS
Claims 1,2,9,10,17, and 18
Independent claim 1 recites, inter alia, a processor to “write at least
the data corresponding to the at least one of the cache lines that will be fully
written without first determining ownership of the sections of the cache
2 We note the contested negative limitation was recited in identical form in
original independent claims 1, 9, and 17. See Spec. 27—29.
3
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Application 14/273,649
memory.” Independent claims 9 (a method) and 17 (a storage device) recite
a substantially identical limitation.
The Examiner finds that Corbal discloses the claimed writing without
first determining ownership. Ans. 3^4. Corbal’s discussion of the prior art
explains that a processor issues a request for ownership (RFO) for a cache
line prior to writing to that cache line. Corbal’s advance relative to the prior
art is said to be that the processor will not waste memory bandwidth fetching
data that will be completely overwritten. Corbal 3:14—15.
To this end, Corbal performs a “CLINITPREF M” instruction that
prefetches a cache line at address M. Id. at 3:19—22. If the cache line is not
in the processor’s local cache, the processor issues an RFO_NODATA
instruction to the other processing cores. If this request is granted by the
other cores and there is a cache hit on another cache, the other processors
invalidate their local copies of the cache line. Id. at 3:24—26. Unlike a
traditional granted RFO and cache hit, the cache line is not provided to the
requesting processing core. Id. at 3:26—28. If the RFO_NODATA is
granted and the cache line is not resident on any of the other processing
cores’ respective caches, the requested cache line is not fetched from
memory 206. Id. at 3:28—30. Instead, a dummy entry is created in the cache
of the processor that issued the RFO_NODATA for the requested cache line
without any “real” data. Id. at 3:31—32. Ideally, the processor completely
writes over the dummy cache line entry through execution of a subsequent
store instruction before any other access of the cache line is desired. Id. at
3:32-34.
The Examiner finds that this disclosure in Corbal corresponds to
writing data to the cache without first determining ownership of the sections
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Application 14/273,649
of cache memory, because the Examiner characterizes the RFO instruction
of Corbal as corresponding to the “prepare sections of the cache memory”
claim limitation, rather than to the “write data” limitation.
We do not agree with the Examiner’s reading of Corbal. The
Examiner has not provided evidence to support the finding that the “without
first determining ownership” limitation does not apply if the Request For
Ownership3 (RFO) instruction “is used to prepare the cache.” See Ans. 7.
The claims under appeal recite explicitly that data is written to “the at least
one of the cache lines that will be fully written without first determining
ownership of the sections of the cache memory.'1'’ Contrary to the Examiner’s
narrow interpretation, we conclude the contested negative limitation is not
temporally constrained to the “writing” portion of the cache’s activity, under
a broad but reasonable interpretation of each independent claim 1, 9, and 17
before us on appeal.4
Because we find that Corbal discloses determining ownership before
writing data, we agree with Appellants that the Examiner erred in rejecting
independent claims 1, 9, and 17. Therefore, we do not sustain the
Examiner’s § 102(a)(1) rejection of independent claims 1, 9, and 17, which
each recite the contested negative limitation in identical form. For the same
reason, we reverse the rejection of associated dependent claims 2, 10, and
18, also rejected under the first-stated anticipation rejection over Corbal.
3 Or RFO_NODATA instruction.
4 We give the contested claim limitations the broadest reasonable
interpretation consistent with the Specification. See In re Morris, 111 F.3d
1048, 1054 (Fed. Cir. 1997).
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Application 14/273,649
Claims 3-8,11-16, and 19-24
We do not sustain the rejection of parent claims 1, 9, and 17 over
Corbal, supra. We have reviewed Jeffers, Kang, and Nayyar, and we find
that these further references do not remedy the aforementioned deficiency of
Corbal. Therefore, we do not sustain the Examiner’s § 103 rejections of
claims 3—8, 11—16, and 19—24, for the same reasons expressed with respect
to parent claims 1, 9, and 17, supra.
CONCLUSION
Corbal does not disclose writing at least the data corresponding to the
at least one of the cache lines that will be fully written without first
determining ownership of the sections of the cache memory.
ORDER
The Examiner’s decision to reject claims 1—24 is reversed.
REVERSED
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