Ex Parte King et al

Patent Trial and Appeal Board

Mar 1, 2016

11756580 (P.T.A.B. Mar. 1, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
111756,580 05/31/2007
97149 7590 03/03/2016
Maschoff Brennan
1389 Center Drive, Suite 300
Park City, UT 84098
FIRST NAMED INVENTOR
Jonathan Paul King
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
F 1002.10l68USO1 1075
EXAMINER
JACOB, OOMMEN
ART UNIT PAPER NUMBER
2637
NOTIFICATION DATE DELIVERY MODE
03/03/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docket@mabr.com
info@mabr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JONATHAN PAUL KING and JAMES D. MCVEY
Appeal2014-003279
Application 11/756,580
Technology Center 2600
Before MAHSHID D. SAADAT, JOHNNY A. KUMAR, and
JON M. JURGOV AN, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-003279
Application 11/756,580
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-8, 10-12, and 14--25. Claims 9 and 13 have been canceled. We
have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
Exemplary Claim
Appellants' invention relates to testing an optoelectronic device.
Spec. i-f 10. Exemplary claim 1 under appeal reads as follows:
1. A method of testing an optoelectronic device,
comprising the following acts:
receiving an electrical test pattern designed to introduce
error into the optoelectronic device, the electrical test pattern
including a digital sum variation of at least 3, between about 16
and about 254 binary digits (bits), at least one run of five or
more consecutive 0 bits and at least one run of five or more
consecutive l bits, and at least one isolated 0 bit surrounded by
runs of 1 bits and at least one isolated 1 bit surrounded by runs
of 0 bits;
converting the electrical test pattern to an optical
waveform;
sampling the optical waveform; and
calculating a penalty, wherein the penalty calculation is
associated with a difference in decibels between a reference
signal to noise ratio (SNR) and an equivalent SNR for the
sampled waveform after propagation through a simulated fiber
channel.
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Application 11/756,580
The Examiner's Rejections1
The Examiner rejected claims 1-3, 5-8, 10-12, and 14--16 under
35 U.S.C. § 103(a) as being unpatentable over Swenson (US 2006/0263084
Al, Nov. 23, 2006) and Basto (US 2004/0230395 Al, Nov. 18, 2004). Final
Act. 3-8.
The Examiner rejected claim 4 under 35 U.S.C. § 103(a) as being
unpatentable over Swenson, Basto, and Lindsay (US 2007/0036084 Al, Feb.
15, 2007). Final Act. 8.
The Examiner rejected claim 17 under 35 U.S.C. § 103(a) as being
unpatentable over Swenson, Basto, and Fennelly (US 2004/0144913 Al,
July 29, 2004). Final Act. 9.
The Examiner rejected claim 18 under 35 U.S.C. § 103(a) as being
unpatentable over Swenson, Basto, and Aulet (US 5,644,417, July 1, 1997).
Final Act. 9-10.
The Examiner rejected claims 19-'23 and 25 under 35 U.S.C. § 103(a)
as being unpatentable over Fennelly and Basto. Final Act. 10-13.
The Examiner rejected claim 24 under 35 U.S.C. § 103(a) as being
unpatentable over Fennelly, Basto, and Aulet. Final Act. 13-14.
1 Throughout this opinion we refer to the Final Office Action ("Final Act.")
mailed Apr. 12, 2013, and the Examiner's Answer ("Ans.") mailed on Nov.
6, 2013.
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Appeal2014-003279
Application 11/756,580
Appellants' Contentions2
1. Appellants contend the electrical test pattern recited in independent
claims 1 and 19 does not represent an optimization of a "range" within the
meaning ofMPEP § 2144.05. App. Br. 9-12; Reply Br. 7-10. Appellants
argue the relevant case law regarding ranges involves temperatures,
concentrations, and size dimensions, which all have upper and lower bounds,
but the case law does not extend to electrical test patterns. 3 Id.
2. Appellants contend the large number of possible test pattern
combinations in an N-bit pattern (e.g., 16-bit pattern has 65,536 possible test
patterns) would require more than routine experimentation to determine the
effectiveness of introducing error for each possible test pattern. App. Br.
12-14.
3. Appellants contend the prior art references do not recognize the
claimed test pattern parameters, including a digital sum variation, runs of 0
or 1 bits, and isolated 0 or 1 bits, as "result-effective variables.'' App. Br.
14--15; Reply Br. 10-12. Appellants further argue the electrical memory test
pattern ofBasto is not a result-effective variable because the pattern is not
designed to introduce error, as no particular test pattern is better or worse for
detection of memory failure. App. Br. 15-16.
4. Appellants contend the rejections of claims 1 and 19 are based on
impermissible hindsight, because no combination of Fennelly, Swenson, and
2 Throughout this opinion we refer to the Appeal Brief ("App. Br.") dated
Sept. 12, 2013, and the Reply Brief ("Reply Br.") dated Jan. 2, 2014.
3 Separate patentability is not argued for dependent claims 2-8, 10-12, 14--
18, and 20-25. App. Br. 6. Except for our ultimate decision, these claims
are not discussed further.
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Application 11/756,580
Basto teaches an electrical test pattern designed to introduce error into an
optoelectronic device. App. Br. 17-18. Appellants argue Basto provides no
indication that the electrical test patterns used to identify failure in a memory
device would be suitable for optoelectronic devices, therefore any reason to
combine the references could only have been gleaned from Appellants'
Specification. Id.
5. Appellants contend the Examiner has not cited a reference to teach the
concept of a digital sum variation, rather the Examiner uses the definition
provided by Appellants with reference to one of the test patterns in Basto,
which is further evidence of impermissible hindsight in the rejections of
claims 1and19. App. Br. 18-19; Reply Br. 12.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments (App. Br. 7-19; Reply Br. 6-12) that the Examiner erred. We
disagree with Appellants' above contentions 1-5. We adopt as our own ( 1)
the findings and reasons set forth by the Examiner in the action from which
this appeal is taken (Final Act. 3-14) and (2) the reasons set forth by the
Examiner in the Examiner's Answer (Ans. 2-8) in response to Appellants'
Appeal Brief. We concur with the conclusions reached by the Examiner.
We highlight and address specific findings and arguments for emphasis as
follows.
As to Appellants' contentions 1-3 that the electrical test pattern
recited in independent claims 1 and 19 does not represent an optimization of
a range, we have considered each of Appellants' contentions, but we are not
persuaded of Examiner error. The Examiner finds Swenson teaches a
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Application 11/756,580
method of testing an optoelectronic device by converting an electrical test
pattern to an optical waveform, and finds Basto teaches generating an
electrical test pattern designed to introduce errors. Final Act. 3--4 (citing
Basto iii! 36-37 and Fig. 4D; see also Basto if 42 and Claim 11, any
combination of test patterns taught in Figs. 4A--4D can be used). The
Examiner finds it would have been obvious to one of ordinary skill in the art
to try the finite number of combinations of test patterns taught by Basto in
order to find the optimal test conditions for the device of Swenson. Final
Act. 4--5.
Further, Appellants have not disclosed specific details of the testing
procedure used to determine the claimed test pattern. See Spec. if 36
("testing has revealed that long runs of consecutive bits tend to cause error
and identify non-compliant optoelectronic devices" (emphasis added)). We
agree with the Examiner's finding that trying a finite number of test pattern
combinations to determine the optimal test pattern, based on Basto; s
teaching of combining test patterns having long runs of ones/zeros and
isolated ones/zeros (Final Act. 4--5), is within the ability of one of ordinary
skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 421
(2007) ("When there is a design need or market pressure to solve a problem
and there are a finite number of identified, predictable solutions, a person of
ordinary skill has good reason to pursue the known options within his or her
technical grasp. If this leads to the anticipated success, it is likely the
product not of innovation but of ordinary skill and common sense. In that
instance the fact that a combination was obvious to try might show that it
was obvious under§ 103.").
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Application 11/756,580
Regarding Appellants' contention 4 that the rejection is based on
impermissible hindsight because the cited references do not teach an
electrical test pattern designed to introduce error into an optoelectronic
device, Appellants' contention does not show error in the Examiner's
rejection. We observe that the claimed test merely identifies defective
devices because Appellants' Specification describes the claimed test pattern
as being designed to indicate whether a device will fail the industry standard
test (Spec. i-f 26). As such, we agree with the Examiner's finding that
Swenson uses various electrical test patterns to identify errors in
optoelectronic devices, and that one of ordinary skill in the art would the
recognize the applicability of Basto's electrical test patterns to Swenson's
optoelectronic device. Ans. 6-7; Final Act. 3-5. Therefore, we are not
persuaded by Appellants' argument that the Examiner's rejection is an
improper hindsight reconstruction, as it does not include knowledge gleaned
only from the Appellants; disclosure, but rather takes into account the prior
art teachings of Swenson and Basto. See In re McLaughlin, 443 F.2d 1392,
1395 (CCPA 1971) ("Any judgment on obviousness is in a sense necessarily
a reconstruction based upon hindsight reasoning, but so long as it takes into
account only knowledge which was within the level of ordinary skill [in the
art] at the time the claimed invention was made and does not include
knowledge gleaned only from applicant's disclosure, such a reconstruction is
proper.").
As to Appellants' contention 5 that the Examiner has not cited a
reference to teach the claimed digital sum variation, we are not persuaded of
Examiner error. The Examiner finds Figure 4D of Basto teaches this
limitation. Final Act. 4. The Examiner used the formula for "digital sum
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Application 11/756,580
variation" provided by Appellants' Specification (Ans. 7-8 (citing Spec.
i-f 38, cumulative sum of 1 bits assigned a +0.5 value and 0 bits assigned a -
0.5 value)) and applied this formula to Basto's Figure 4D, having long runs
of 1 bits and 0 bits. In their Reply Brief, Appellants have not rebutted this
finding persuasively. We agree with the Examiner's finding that the
combination of Swenson and Basto teaches the claimed test pattern, as
discussed with respect to contentions 1--4 supra. We also agree with the
Examiner's finding that, using Appellants' defined formula for digital sum
variation, the test pattern of Swenson and Basto will result in the claimed
digital sum variation. Therefore, in the absence of persuasive rebuttal
evidence or argument to persuade us otherwise, we adopt the Examiner's
findings and underlying reasoning, which are incorporated herein by
reference.
Accordingly, we sustain the Examiner's rejection of independent
claims 1 and 19.
DECISION
The Examiner's rejections of claims 1-8, 10-12, and 14--25 are
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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