Ex Parte Kimura

Patent Trial and Appeal Board

Apr 28, 2017

12754936 (P.T.A.B. Apr. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/754,936 04/06/2010 Hajime KIMURA 0756-8822 7640
31780 7590 05/02/2017
Robinson Intellectual Property Law Office, P.C.
3975 Fair Ridge Drive
Suite 20 North
Fairfax, VA 22033
EXAMINER
KIM, JAY C
ART UNIT PAPER NUMBER
2815
NOTIFICATION DATE DELIVERY MODE
05/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ptomail @ riplo .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HAJIME KIMURA1
Appeal 2015-006448
Application 12/754,936
Technology Center 2800
Before CARLA M. KRIVAK, CAROLYN D. THOMAS, and
JOHN R. KENNY, Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from a non-final rejection
of claims 1—11 and 16—26. We have jurisdiction under 35 U.S.C. § 6(b). An
oral hearing was conducted April 6, 2017.
We affirm.
1 The Real Party in Interest is Semiconductor Energy Laboratory Co., Ltd.,
App. Br. 4.
Appeal 2015-006448
Application 12/754,936
STATEMENT OF THE CASE
Appellant’s invention is directed to “a display device or a
semiconductor device which is formed by single-crystal being transferred to
a glass substrate” (Spec. 11).
Independent claim 1, reproduced below, is exemplary of the subject
matter on appeal.
1. A semiconductor device comprising:
a first semiconductor layer;
a first insulating layer over the first semiconductor layer;
a first conductive layer and a second conductive layer which are over
the first insulating layer;
a second insulating layer over the first conductive layer and the
second conductive layer; and
a second semiconductor layer over the second insulating layer,
wherein the first semiconductor layer comprises crystalline silicon,
and
wherein the second semiconductor layer comprises an oxide
semiconductor layer, the oxide semiconductor layer forming a channel
formation region of a transistor.
REFERENCES and REJECTIONS
The Examiner rejected claims 1—11 and 16—26 under 35 U.S.C. §112.
The Examiner rejected claims 1—6, 9-11, 16—21, and 23—26 under 35
U.S.C. § 102(e) as anticipated by Choi (US 2010-0182223 Al; July 22,
2010).
The Examiner rejected claims 7, 8, and 22 under 35 U.S.C. § 103(a)
based upon the teachings of Choi.
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Application 12/754,936
ANALYSIS
We initially note the Examiner finds Appellant is not in possession of
the claimed “first semiconductor layer comprises crystalline silicon, and
wherein the second semiconductor layer comprises an oxide semiconductor
layer, the oxide semiconductor layer forming a channel formation region of
a transistor” (Non-Final Act. 3).
Appellant contends the main issue is “whether Appellant’s original
disclosure supports written description and enablement for the pending
claims” (App. Br. 18). If so, Choi is no longer a prior art reference (id.). To
support this contention, Appellant asserts paragraphs 43 and 37 of the
Specification support the independent claims 1,2, and 16 limitation reciting
first and second semiconductor layers (App. Br. 6—10).
Paragraph 43 cited by Appellant as support for the different materials
used for the first and second semiconductor layers of the semiconductor
device recites “A transistor including a compound semiconductor or an
oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or
SnO, a thin film transistor obtained by thinning such a compound
semiconductor or an oxide semiconductor, or the like can be used.”
Paragraph 37 recites “Note that various types of transistors can be used as a
transistor, without limiting to a certain type. For example, a thin film
transistor (TFT) including a non-single-crystal semiconductor film typified
by amorphous silicon, polycrystalline silicon, microcrystalline (also referred
to as semi-amorphous) silicon, or the like can be used” (emphasis added).
Thus, Appellant contends the broadest reasonable interpretation of these
limitations in the Specification “is an integrated semiconductor device
having at least two semiconductor layers (or two transistors) that differ in
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Application 12/754,936
properties (e.g., broad categories of single-crystal and other than single­
crystal)” (App. Br. 8—9).
Further, Appellant contends the Examiner’s view is unreasonably
narrow and improperly limited to a specific embodiment (App. Br. 9). That
is, Appellant asserts, the same type of semiconductor (an oxide
semiconductor) cannot be “used for both the first and second transistor”
because it would frustrate the “purpose of having first and second transistors
with different properties” (id. ). Additionally, Appellant asserts an ordinarily
skilled artisan would understand that first and second semiconductors having
different properties can be formed by different materials (App. Br. 9; Reply
Br. 5). We do not agree with Appellant’s contentions.
Paragraph 43 of Appellant’s Specification states a transistor may be
made of various materials. Paragraph 37 states the “various types of
transistors can be used as a transistor, without limiting to a certain type. For
example, a thin film transistor (TFT) including a non-single-crystal
semiconductor film typified by amorphous silicon, polycrystalline silicon,
microcrystalline (also referred to as semi-amorphous) silicon, or the like can
be used” (emphasis added). These portions of the Specification merely state
the transistor or transistors can be made of various materials, not that each
transistor is made of a different material.
MPEP 2162 recites in part:
the patentee must disclose in the patent sufficient information to
put the public in possession of the invention and to enable those
skilled in the art to make and use the invention. The applicant
must not conceal from the public the best way of practicing the
invention that was known to the patentee at the time of filing the
patent application. Failure to fully comply with the disclosure
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Appeal 2015-006448
Application 12/754,936
requirements could result in the denial of a patent, or in a holding
of invalidity of an issued patent.
We note Appellant’s paragraph 12 states “[a] property of the first
semiconductor layer is different from a property of the second
semiconductor layer” (emphases added). Thus, the Specification supports
the first and second semiconductor layers have different properties.
However, it does not support the first semiconductor layer being formed of
a material different from the second semiconductor layer. Materials and
properties are not necessarily the same. That is, it is not necessary that the
material be different to have different properties; the same material can
have different properties depending on doping, charge applied, etc.
Therefore, Appellant’s Specification does not describe the claim limitations
“the first semiconductor layer comprises crystalline silicon, and wherein the
second semiconductor layer comprises an oxide semiconductor layer.”
Appellant has not convinced us (nor shown us where) the Specification
supports this limitation; properties are what is disclosed in Appellant’s
Specification. It does not necessarily follow that each semiconductor layer
be formed of a different material that must have a different property,
particularly since the same material, depending on doping, charge applied,
etc., would have different properties.
Therefore, we agree with the Examiner that “while the original
disclosure teaches similar material compositions having different material
properties for the first and second semiconductor layer, the original
disclosure did not teach two completely dissimilar materials disposed at two
specific positions of the overall semiconductor device structure, i.e. a single
crystalline silicon layer for the first semiconductor layer 102 and an oxide
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Application 12/754,936
semiconductor layer for the second semiconductor layer 202A in Fig. 6 of
current Application” (Ans. 4; see also Ans. 7—8). Thus, we agree with the
Examiner, Appellant’s Specification does not meet the written description
requirement. Because the claims are not supported by Appellant’s original
Specification in Serial No. 12/213,036, this Application is not afforded the
filing date of that Application, and Choi is a prior art reference. As
Appellant has not addressed the Examiner’s rejection of the claims over
Choi, we summarily sustain the 35 U.S.C. §§ 102 and 103 rejections.
DECISION
The Examiner’s decision rejecting claims 1—11 and 16—26 under 35
U.S.C. § 112, first paragraph is affirmed.
The Examiner’s decision rejecting claims 1—6, 9—11, 16—21, and 23—
26 under 35 U.S.C. § 102(e) is affirmed.
The Examiner’s decision rejecting claims 7, 8, and 22 under 35 U.S.C.
§ 103(a) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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