Ex Parte Kim et al

Patent Trial and Appeal Board

Oct 27, 2017

13162702 (P.T.A.B. Oct. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/162,702 06/17/2011 Dae Suk KIM SN101.HY140U-0T 8070
96767 7590 10/31/2017
William Park & Associates LTD.
930 N. York Road, Suite 201
Hinsdale, IL 60521
EXAMINER
O TOOLE, COLLEEN J
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
10/31/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAE SUK KIM, JONG CHERN LEE, and
SANG JIN BYEON
Appeal 2017-000648
Application 13/162,702
Technology Center 2800
Before TERRY J. OWENS, MARKNAGUMO, and
MONTE T. SQUIRE, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’
rejection of claims 1, 4—6, 8, 9, 11—21 and 23—30. We have jurisdiction
under 35 U.S.C. § 6(b).
The Invention
Wu discloses a semiconductor apparatus. Claim 1 is illustrative:
1. A semiconductor apparatus comprising:
a master chip;
first to nth slave chips;
first to nth slave chip ID generating units disposed
respectively in the first to nth slave chips and connected in series
to each other, each of the first to nth slave chip ID generating
Appeal 2017-000648
Application 13/162,702
units being configured to add a predetermined code value to an
mth operation code to generate an (m+l)th operation code;
a master chip ID generating unit disposed in the master
chip to generate a variable first operation code from one of an
initial code having a plural bits and a variable code having a
plural bits in response to a select signal; and
a selecting unit outputs the variable code when the select
signal is activated and outputs the initial code when the select
signal is deactivated,
wherein 'n' is an integer that is equal to or greater than 2,
and'm' is an integer that is equal to or greater than 1 and equal
to or smaller than 'n'.
The Reference
Wu US 8,269,521 B2 Sept. 18,2012
The Rejection
Claims 1, 4—6, 8, 9, 11—21 and 23—30 stand rejected under
35 U.S.C. § 102(e) over Wu.
OPINION
We reverse the rejection. We need address only the independent
claims (1,15 and 21). Those claims require a semiconductor apparatus
comprising a master chip unit which can generate a first operation code from
one of an initial code and a variable code according to a select signal, output
the variable code when the select signal is activated and output the initial
code when the select signal is deactivated.
“Anticipation requires that every limitation of the claim in issue be
disclosed, either expressly or under principles of inherency, in a single prior
art reference.” Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868
F.2d 1251, 1255-56 (Fed. Cir. 1989).
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Appeal 2017-000648
Application 13/162,702
Wu discloses a multi-chip stacked system comprising a
controller (110) having a layer number detector (112) which controls a
PMOS transistor (PI) according to the timing of a chip select signal (CCS)
(col. 11,11. 17—19). In an automatic chip number detection mode, before the
chip select signal (CCS) transits to “0000” the layer number detector (112)
controls the PMOS transistor (PI) to charge a signal line (113) (col. 11,
11. 23—25; Fig. 12). When the chip select signal (CCS) has transited to
“0000” the layer number detector (112) turns the PMOS transistor (PI) off, a
first seed code (SCI) and a first ID code (ID1) are “1111”, and a chip select
signal (CS1) output by a first chip die (DIE_l)’s activation logic
unit (122_1) is logic 1, so the first chip die (DIE_l)’s function module is
activated and that die’s NMOS transistor (Nr.v) turns on to discharge the
signal line (113) and thereby cause the layer number detector (112) to detect
that the first chip die (DIE_1) is to be activated when the chip select signal
(CCS) is “0000” (col. 11,11. 25-36; Fig. 12). When all chip select signal
(CCS) logic modes have been tested, the automatic chip number detection
mode ends and the system returns to the normal operation mode wherein the
layer number detector (112) may output logic 1 to turn off the PMOS
transistor (PI) (col. 11,11. 11—12, 39-42).
The Examiner finds that Wu’s first seed code (SCI) corresponds to
the Appellants’ initial code and variable code and that Wu generates that
code “in response to a select signal (controlling PI)” (Final Act. 2; Ans. 2—
4).
Wu’s layer number detector (112) turns the PMOS transistor (PI) on
to charge the signal line (113) and then turns that transistor off (col. 11,
11. 23—27). First seed code (SCI) is formed from the chip select
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Appeal 2017-000648
Application 13/162,702
signal (CCS), not in response to the turning on and off of the PMOS
transistor (PI) (col. 10,11. 38—39; Fig. 12).
The Examiner, therefore, has not established that Wu discloses, either
expressly or inherently, every limitation of the Appellants’ claims.
Accordingly, we reverse the rejection.
DECISION/ORDER
The rejection of claims 1, 4—6, 8, 9, 11—21 and 23—30 under
35 U.S.C. § 102(e) over Wu is reversed.
It is ordered that the Examiner’s decision is reversed.
REVERSED
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