Ex Parte Khoche et al

Patent Trial and Appeal Board

Mar 12, 2014

11895590 (P.T.A.B. Mar. 12, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/895,590 08/24/2007 Ajay Khoche ATSS-0194-01.01US 2109
109838 7590 03/12/2014
Advantest c/o Murabito Hao & Barnes LLP
Two North Market Street
Third Floor
San Jose, CA 95113
EXAMINER
MALDONADO, JULIO J
ART UNIT PAPER NUMBER
2898
MAIL DATE DELIVERY MODE
03/12/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte AJAY KHOCHE and DUNCAN GURLEY
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Appeal 2012-001053
Application 11/895,590
Technology Center 2800
____________________

Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.

TIMM, Administrative Patent Judge.

DECISION ON APPEAL

Appellants seek review of the Examiner’s decision to reject claims 1-
29 under 35 U.S.C. § 103(a) as obvious. Specifically, the Examiner rejects
claims 1-3, 5-19, and 21-29 as obvious over Beaulieu1 in view of Chen.2 To
reject claims 4 and 20, the Examiner adds Ohshima.3 We have jurisdiction
under 35 U.S.C. §§ 6(b) and 134.
We AFFIRM-IN-PART.

1 Beaulieu et al., US 6,993,405 B2, patented Jan. 31, 2006.
2 Chen, US 2006/0132167 A1, pub. June 22, 2006.
3 Ohshima et al., US 2006/0068512 A1, pub. Mar. 30, 2006.
Appeal 2012-001053
Application 11/895,590
2

The claims are directed to a method and apparatus for testing wafers
(see, e.g., Claims 1 and 18). Claims 1 and 18 are reproduced below:
1. A method of testing wafers, said method comprising:
providing a wafer carrier;
disposing a wafer in said wafer carrier;
moving said wafer carrier and said wafer between a first
manufacturing location and a second manufacturing location;
testing said wafer while said wafer is disposed in said
wafer carrier and after completion of manufacturing operations
at said first manufacturing location and before manufacturing
operations at said second manufacturing location.
(Claims App’x at Br. A-1.)
18. An apparatus for testing wafers, said apparatus
comprising:
a wafer carrier;
a test circuit disposed on said wafer carrier, said test
circuit configured to perform testing on a wafer being carried
by said wafer carrier after completion of manufacturing
operations at a first manufacturing location and before
commencement of manufacturing operations at a second
manufacturing location.
(Claims App’x at Br. A-4.)

OPINION
To support the rejection of claim 1, the Examiner relies upon
Beaulieu’s teaching of providing a wafer carrier, disposing a wafer within
the carrier, moving the wafer-containing carrier, and monitoring the internal
environment of the wafer-containing carrier between manufacturing
Appeal 2012-001053
Application 11/895,590
3
operations (Ans. 3-4). The Examiner acknowledges that Beaulieu does not
disclose testing the wafer while it is in the carrier and in transit between the
manufacturing operations (Ans. 4). The Examiner instead relies upon
Chen’s teaching of testing a wafer using an on-wafer, wireless built-in self
test (BIST) circuit (id.). Based on these teachings, the Examiner determines
that “it would have been obvious to one of ordinary skill in the art at the
time of the invention to modify Beaulieu with the wafer testing as taught by
Chen for improved device testing.” (Id., citing Chen ¶ 0017).
We agree with Appellants that the Examiner’s proposed combination
would not have suggested testing the wafer while the wafer was being
transported by the carrier between manufacturing operations as required by
claim 1 (Br. 14).
Beaulieu monitors the internal environment of the wafer carrier (e.g.
temperature, pressure, humidity, particulate count, etc.) and events (e.g.,
vibration, accelerations, shocks, light intrusion, etc.), using a wireless micro-
sensor (Beaulieu, col. 2, ll. 50-55; col. 3, ll. 27-32; col. 6, ll. 6-24). This
monitoring takes place while the wafers are within the carrier traveling from
first manufacturing tool 315A to a second manufacturing tool 315B, but
Beaulieu specifically discloses that testing occurs within the manufacturing
tools (see Beaulieu, col. 5, l. 49 to col. 6, l. 2 (indicating that manufacturing
tools 315A and 315B may be inspection or measurement tools)).
Chen also conducts testing within a tool 700 (Chen ¶ 0067-68 and Fig.
7A). While, as pointed out by the Examiner, the wafer of Chen is in transit
within the tool 700, the wafers are not within a carrier when they are within
the tool (see Fig. 7A (showing the transit of single wafers 300)).
The Examiner has not established an evidentiary basis for the finding
of a suggestion of testing the wafer while the wafer is disposed in the wafer
Appeal 2012-001053
Application 11/895,590
4
carrier and in transit between the tools that is based upon the teachings of the
prior art or knowledge within the prior art. Therefore, we do not sustain the
rejection of claim 1, and those claims depending from claim 1, based upon
the combination of Beaulieu and Chen. Because the deficiency is not cured
in the rejection of claim 4 over Beaulieu, Chen, and Ohshima, we further do
not sustain that rejection.
We note that claim 18 is directed to an apparatus, not a process and is
of different scope than claim 1. Moreover, with regard to claim 18, the
Examiner further finds that circuits 190A and 190B are test circuit elements
(Ans. 9).
Claim 18 requires a test circuit that is configured to perform testing
and that is disposed on a wafer carrier.
Figures 3 and 4 of Beaulieu depict a microsensor 140B including
integrated circuits 190A and discrete circuit elements 190B (Beaulieu, col. 4,
ll. 12-27). The microsensor 140 of Beaulieu is within a wafer carrier 100
(Beaulieu, Figs. 1A and 1B; col. 3, ll. 16-32).
Appellants do not dispute the Examiner’s finding that circuits 190A
and 190B are test circuits (Br. 15). Moreover, there is no question that the
circuits are disposed on the wafer carrier 100. Therefore, Appellants have
not identified a reversible error in the Examiner’s rejection of claim 18 or
any of the claims dependent therefrom.

CONCLUSION
We sustain the Examiner’s rejection of claims 18-29, but we do not
sustain the Examiner’s rejection of claims 1-17.
Appeal 2012-001053
Application 11/895,590
5

DECISION
The Examiner’s decision is affirmed-in-part.

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).

AFFIRMED-IN-PART
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