Ex Parte Keil et al

Patent Trial and Appeal Board

Jul 23, 2018

13303386 (P.T.A.B. Jul. 23, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/303,386 11/23/2011
91286 7590 07/25/2018
Harness, Dickey & Pierce, P.L.C. (Lam)
P.O. Box 828
Bloomfield Hills, MI 48303
FIRST NAMED INVENTOR
Douglas Keil
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
NVLS003705 4858
EXAMINER
JAVED, MIRZA ISRAR
ART UNIT PAPER NUMBER
1718
NOTIFICATION DATE DELIVERY MODE
07/25/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
sstevens@hdp.com
troymailroom@hdp.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE
THE PATENT TRIAL AND APPEAL BOARD
Ex parte DOUGLAS KEIL, 1
Edward Augustyniak, Karl Leeser, and Mohamed Sabri
Appeal2017-009725
Application 13/303,386
Technology Center 1700
Before MARK NAGUMO, KAREN M. HASTINGS, and LILAN REN,
Administrative Patent Judges.
NAGUMO, Administrative Patent Judge.
DECISION ON APPEAL
Douglas Keil, Edward Augustyniak, Karl Leeser, and Mohamed Sabri
("Keil") timely appeal under 35 U.S.C. § 134(a) from the Final Rejection2 of
claims 1-12 and 16-24. 3 We have jurisdiction. 35 U.S.C. § 6. We reverse
for reasons well-stated by Keil.
1 The real party in interest is identified as Novellus Systems, Inc. (Appeal
Brief, filed 3 March 2017 ("Br."), 4.)
2 Office Action mailed 7 October 2016 ("Final Rejection"; cited as "FR").
3 Remaining copending claims 13-15 and 25-33 have been withdrawn from
consideration by the Examiner, and are not before us.
Appeal2017-009725
Application 13/303,386
A. Introduction4
OPINION
The subject matter on appeal relates to systems for reducing parasitic
plasma in semiconductor processing. The '386 Specification explains that in
one semiconductor substrate processing system, radio frequency power to
create a plasma in the gases introduced to chamber 1025 from sources 144 is
applied to substrate holder 134, as shown in Figure 1, below:
124
HFRF LFRF
Generator Generator
MaWhing
l.!el\\lork
126
142
136 L=-:;:f::=::=~ 12_!,r-134
130
136-
/100
102
{Figure 1 shows a substrate processing chamber with RF power applied to
pedestal substrate holder 134.}
4 Application 13/303,386, Mechanical suppression of parasitic plasma in
substrate processing chamber, filed 23 November 2011, claiming the benefit
of a provisional application filed 17 October 2011. We refer to the
"'386 Specification," which we cite as "Spec."
5 Throughout this Opinion, for clarity, labels to elements are presented in
bold font, regardless of their presentation in the original document.
2
Appeal2017-009725
Application 13/303,386
As indicated by grounded pedestal support 135 in Figure 1, parts of
the substrate holder are conductive. If the grounded parts are too near the
RF "hot" surfaces, and thus are at a very different electrical potential from
the RF hot surface, undesired "parasitic" plasmas may be formed between
the conductive surface as the RF hot surface. (Spec. 10 [0035].) Providing a
sufficiently thick dielectric material to provide low capacitive coupling (i.e.,
less than 100 pF) is said to "typically result[] in very thick layers (many cm
in size) that are either not practical or expensive to implement." (Id.)
The Specification discloses that the dielectric can be provided as
plural (N) thin layers or disks of dielectric separated by gaps between the
conductive layer and the first dielectric layer, between two or more dielectric
layers, and between the last dielectric layer and the RF electrode. (Id.) The
equivalent circuit is said to be multiple capacitors connected in series. In the
words of the Specification, "[t]he net capacitance of the series connection of
the equivalent capacitors is lower than the lowest capacitor value[] ...
[which] will generally correspond to the capacitance associated with the gap
between the N dielectric layers." (Id. at 10-11 [[0036].)
The RF power may also be applied to the showerhead electrode
(id. at 7 [0025]), and capacitive coupling may be reduced in a similar
manner. An example of the invention applied for a substrate pedestal that
functions as the RF plasma generator is shown in Figure 2A, next page, left,
and applied to a showerhead that functions as the RF plasma generator in
Figure 5, next page, right.
3
Appeal2017-009725
Application 13/303,386
{Figure 2A (left) and Figure 5 (right) are shown below}
-··
/ I
o-.'L,3;:i} ese.-! _.I RS.4
1.n' .., l-f,SS
~·~~~.JL"---+-' ----------+--") '-los--__ 1 ~-
{Fig. 2A: gapped dielectric layers 250 at pedestal}
{Fig. 5: gapped dielectric layers 650 at showerhead}
In the pedestal version shown in Figure 2A, RF power is supplied to
electrode 128, which is embedded in the nonconductive ( ceramic or quartz)
pedestal platen 252. The conducting structures-adaptor 220, collar 230,
and structure 240-are typically grounded, so dielectric layers 250,
separated by gap g from one another and from platen 252 and
from conductive structure 240 provide the low capacitive coupling.
In the showerhead version shown in Figure 5, RF power is supplied to
conductive head 604 and stem 606, which are supported by insulating
supporting portion 644 to top portion 646 of the processing chamber, which
is typically grounded. (Id. at 14 [0046]-[0047].) Low capacitive coupling is
provided by gapped dielectric layers 650. (Id. at [0046].)
4
Appeal2017-009725
Application 13/303,386
Claim 1 is representative and reads:
A system for reducing parasitic plasma in a semiconductor
process, compnsmg:
a first surface of a conducting structure; and
a plurality of dielectric layers that are vertically stacked
between an electrode and the first surface,
wherein the first surface and the electrode have
substantially different electrical potentials,
wherein the plurality of dielectric layers defines:
a first gap between the electrode and one of the
plurality of dielectric layers,
a second gap between adjacent ones of the plurality of
dielectric layers, and
a third gap between a last one of the plurality of
dielectric layers and the first surface, and
wherein a number of the plurality of dielectric layers and
sizes of the first gap, the second gap and the third gap are
selected to prevent parasitic plasma between the first
surface and the electrode during the semiconductor process.
(Claims App., Br. 25; some indentation, paragraphing, and emphasis added.)
Remaining independent claim 16 is drawn to a pedestal system for
semiconductor processing. (Id. at 28-29.)
5
Appeal2017-009725
Application 13/303,386
The Examiner maintains the following grounds of rejection 6, 7, 8 :
A. Claims 1-3 stand rejected under 35 U.S.C. § I03(a) in view
of the combined teachings of Choi9 and Hayashi. 10
(The remaining claims dependent on claim 1, namely claims 4--12,
stand rejected further in view of eight additional references in various
combinations. (FR 9-15.))
B. Claims 16-18, 20, 21, and 24 stand rejected under
35 U.S.C. § I03(a) in view of the combined teachings of
Choi, Hayashi, and Norrbakhsh. 11
(The remaining claims dependent on claim 16, namely claims 19, 22,
and 23, stand rejected further in view of various combinations of five
additional references selected from those relied on in Rejections A. (FR 15-
22.))
6 Examiner's Answer mailed 19 May 2017 ("Ans.").
7 Because this application was filed before the 16 March 2013, effective
date of the America Invents Act, we refer to the pre-AIA version of the
statute.
8 A rejection of claims 1, 5, 6, and 22 under 35 U.S.C. § 112(2) for
indefiniteness (FR 6) has been withdrawn by the Examiner. (Ans. 2, ,r 2.)
9 Jong Yong Choi, Dry etching apparatus, U.S. Patent Application
Publication 2010/0000684 Al (2010), based on an application
filed 2 July 2009.
10 Daisuke Hayashi, Substrate processing apparatus, and substrate stage
used therein, U.S. Patent Application Publication 2009/0078694 Al (2009).
11 Hamid Norrbakhsh et al., Correction of wafer temperature drift in a
plasma reactor based upon continuous water temperature measurements
using an in-situ wafer temperature optical probe, U.S. Patent Application
Publication 2002/0048311 Al (2002).
6
Appeal2017-009725
Application 13/303,386
B. Discussion
The Board's findings of fact throughout this Opinion are supported by
a preponderance of the evidence of record.
The Examiner holds that it would have been obvious to substitute the
plural but not vertically stacked layers of dielectric 164 disclosed by Choi in
dry etching apparatus 100 illustrated in Figure 1, below left, with the
vertically stacked dielectric layers 220 disclosed by Hayashi in Figure 1,
below right.
{ Choi, Fig. 1: dry etching
apparatus with RF-platen 160
generated plasma to etch
substrates 130 (Choi 2 [0046])}
~·a;.:s·siirri'i, 100
112 , .• t ... J>OURCE i--~-'"' 114 ,, 104
'.~:j~ ~ n:-~~ i •.... 3 ..... ,
I@ ® 7);,
• ®
©
®
{'ff;l
®l
® @')..- 1J!j
~- 146 @
+ v .. t~====c=t,;:' ~7--7,
-<;'' / .. 102
~· ., .. 142
~
{ (Hayashi, Fig. 1: RF-coil induced
plasma to process substrate W on
heated [124] stage 120
(Hayashi 3 [0037])}
The Examiner explains that it would have been obvious to combine the
teachings of Choi and Hayashi because both are "analogous arts to substrate
processing." (FR 8, ,r 32.) With regard to the rejection of claim 8, the
7
Appeal2017-009725
Application 13/303,386
Examiner finds that "Choi, Hayashi and Norrbakhsh are analogous arts to
substrate support apparatus." (Id. at 13, ,r 62.)
The difficulty with the Examiner's analysis, as Keil points out
(Br. 11-13), is that the dielectric layers 222 described by Hayashi are heat
shields designed to prevent heater 124 in stage 120 from overheating the
bottom 128 and causing "thermal damage to components disposed at the
bottom 128" (Hayashi 4 [0045]). The Examiner has not identified a similar
issue described by Choi, and has not explained why a similar issue would
have been expected to be a problem by a person having ordinary skill in the
art. Nor has the Examiner established any other reason to dissect the
dielectric layer 164 described by Choi into layers separated by gaps.
The "analogous art" analysis merely indicates whether a person
having ordinary skill in the art would have considered a prior art teaching.
A reference in the same art would not be discarded without further
consideration-but of course not all references in the same art would
necessarily be applied to demonstrate obviousness of the claimed invention.
Rather, the second criterion of the analogous art test, i.e., whether the prior
art reference is reasonably pertinent, must also be applied in the
determination of obviousness. The second criterion of reasonable pertinence
applies if the reference "is one which, because of the matter with which it
deals, logically would have commended itself to an inventor's attention in
considering his problem." In re Clay, 966 F.2d 656, 659 (Fed. Cir. 1992).
Put another way, the Examiner has not shown that the teachings of Hayashi
would have been considered reasonably pertinent to any teaching or
suggestion disclosed by Choi.
8
Appeal2017-009725
Application 13/303,386
The Examiner has not relied on any of the remaining references to
cure the defects of Choi and Hayashi relative to the claimed subject matter.
We therefore reverse.
C. Order
It is ORDERED that the rejections of claims 1-12 and 16-24 are
reversed.
REVERSED
9